Technical parameters.
Brand: Xilinx
Model: XC2C128-7VQ100I
Package: QFP-100
Lot Number: 21+
Quantity: 10000
Manufacturer: Xilinx
Product Category: CPLD - Complex Programmable Logic Devices.
Large number of batteries: 128
Number of logical array blocks – lab: 8
Maximum operating frequency: 244 MHz
Propagation Delay – Max: 57 ns
Number of inputs and outputs: 80 iO
Working Supply Voltage: 18 v
Minimum operating temperature: -40 C
Maximum operating temperature: +85 C
Installation style: SMD SMT
Encapsulation Cabinet: VQFP-100
Serial: XC2C128
Humidity sensitivity: yes
Operating supply current: 19 ua
Supply Voltage - Max: 19 v
Supply voltage - min: 17 v
The CoolRunner II CPLD is a highly uniform family of fast, low-power CPLDs. The underlying architecture is the traditional CPLD architecture, which combines macro units into functional blocks (FBs) that interconnect with the global routing matrix Xilinx Advanced Interconnect Matrix (AIM). FB uses a Programmable Logic Array (PLA) configuration that allows all product terms to be routed and shared between any macro cell of FB. The design software can efficiently synthesize and optimize the logic that is then suitable for FB and linked to the ability to utilize a very high percentage of equipment resources. The software easily and automatically manages design changes, leveraging the 100% deployability of the programmable logic array within each FB. This extremely rugged building block provides the industry's highest pin retention over a very wide range of design conditions. The architecture is explained in more detail through a discussion of the underlying FBS, logic, and interconnects. The design software automatically manages these device resources, allowing users to express their designs using completely common constructs without knowing the details of these architectures. More advanced users can utilize these details to gain a more thorough understanding of the choice of software and guide its results.
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