Introduction
In the modern chip manufacturing process, photolithography is a very important step, and the process uses a camera-like principle, and the light emitted by the lithography machine is imaged on the wafer through a reticle with a pattern, so as to realize the transfer of the circuit diagram to the wafer. Ideally, the imaging pattern on the wafer would be exactly the same as the layout design on the reticle. However, when the key size of the reticle pattern is less than the wavelength, the imaging on the wafer will be distorted due to the diffraction effect, so that it is not very consistent with the layout pattern of the reticle, and then it is necessary to calculate the photolithography OPC (optical proximity correction) technology to correct the pattern of the reticle, so as to ensure that the pattern printed on the wafer conforms to the original design.
From the beginning of its establishment, Dongfang Jingyuan has focused on the field of computational lithography and launched the Pangen platform. After nearly a decade of development, Pangen has become a platform that integrates the complete functional chain of precise processes**, DRC, SBAR, OPC, LRC, DPT and SMO. At the same time, through the abundant and large number of production line applications, Dongfang Jingyuan has become a pioneer and leader in the field of computational lithography in China. Recently, combined with the pain points of industrial application and development, Dongfang Jingyuan has launched two new products, Pangen DMC and Pangen DFO, and this article will introduce the research and development background, application and achievements of these two products in detail.
pangen dmc——
Provides a more comprehensive manufacturability check based on rapid process feedback.
With the evolution of technology nodes, the process itself becomes more and more complex, and it is more and more difficult for designers to have a comprehensive and systematic understanding of the process, resulting in repeated iterations of new products in the process side tape-out, and a longer yield ramping, which increases the cost of chip production and prolongs the time to market. According to McKinsey statistics, it takes about 12 to 18 months to iterate on new products in the semiconductor industry from tape-out to final yield ramp up.
*From McKinsey & Company).
Based on the solid computational lithography platform Pangen and rich industrial practical experience, Dongfang Jingyuan has innovatively developed the Pangen DMC (Design Manufacturability Check) product, which is embedded with D2C (Design to Contour) fast lithography feedback engine, which can integrate the full set of FAB OPC The Recipe solution is packaged in the form of an AI model, so that users can quickly and accurately estimate the contour on the final silicon wafer of the design based on the original design, and then predict the potential risks of the design layout in advance.
The D2C engine can accurately capture the behavior of the entire set of OPC recipes, and give Contour results that are very close to the full OPC recipes. As can be seen from the figure below, for the metal and VIA process layers with different geometric characteristics, the Contour given by D2C and the Contour given by the complete OPC recipe are almost fitted together, and the results are very close even if the PV Band (Peak and Valey Band) under multiple process conditions is comprehensively calculated.
Taking a complete 28nm RISC-V Full Chip layout as an example, the difference between the Contour given by D2C and the Contour given by the complete OPC Recipe under different process conditions (PW conditions) is basically less than 1nm, and the computing speed is much higher than that of the complete OPC Recipe, and the current version can be measured to be about 80 times faster.
As process technology becomes more and more complex, it is difficult to cover all aspects of the entire process by relying on abstract rules alone, so a design layout that has passed the rule-based DRC (Design Rule Check) check does not mean that it can perform well on the process side. The Pangen DMC can estimate the final lithography of the design layout and provide feedback on the process side in a more comprehensive and intuitive way. In addition, the DRC check only tells a black-and-white conclusion about whether or not there is a violation, and it is impossible to know how much of an impact a certain level of violation will have on the process side. The Pangen DMC model-based model presents the impact to the user in a very visual way, helping the user to weigh the violation treatment according to the situation in practice. Therefore, whether it is for the manufacturing side or the design side, this product can be used as a very powerful supplement to the existing DRC (Design Rule Check) tool, on the basis of respecting the customer's existing workflow, to help customers more comprehensively discover the risks of process manufacturability in the layout in addition to the DRC inspection, so as to accelerate iteration, reduce time cost, and enable new chip products to increase yield faster in the tape-out process and bring them to market earlier.
pangen dfo——
Effectively eliminate dead pixels and provide a more thorough OPC solution.
When the fab performs OPC, it will develop OPC recipes based on the characteristics of each process layer layout of specific technology nodes, such as OPC recipes for the metal layer of 28nm technology nodes. An OPC recipe is essentially a set of optimization strategies and parameters that transform the raw layout of the entire process layer of the input into a reticle pattern that can be imaged on the silicon wafer as envisioned. OPC Recipe will consider the diverse graphics input under the technology node when developing, and perform lithography ** detection (LRC) after OPC optimization of the design layout, and if the detection finds dead pixels, the OPC Recipe will be iteratively improved, so as to make the OPC Recipe fully cope with various design layouts as much as possible. Once the OPC recipe is finalized, it will move from the R&D department of the fab to the mass production department and put into mass production.
In practice, OPC recipes may not be able to cover the patterns of some locations of the layout, and the output reticle graphics cannot give the expected imaging results, resulting in dead pixels (hot spots) and affecting the final chip yield, which is a practical pain point that the fab needs to face. At this time, it is necessary to make local modifications to the reticle pattern according to the feedback from the lithography ** detection (LRC), that is, mask repair.
Mask repair can effectively help OPC engineers eliminate dead pixels, but it is possible to modify the mask too much, resulting in extreme graphics shapes, which are too sensitive to process disturbances in mask manufacturing and create new problemsAnd in some cases, the topography of the design layout will naturally lead to poor imaging quality there, and it is difficult to converge to a more ideal result after repeated iterations of repair mask
On the basis of the existing computational lithography platform Pangen, Dongfang Jingyuan innovatively expands local mask repair to local design and fine-tuning, and launches Pangen DFO (Defect Free OPC) products, which can provide a more thorough OPC solution with a progressive strategy and continuous automatic checking and filling of gaps. In practice, for the dead pixels found in the whole chip lithography ** detection (LRC), the method of local mask repair is first adopted, and if it can be solved directly, the treatment of the dead pixels is completed. If it cannot be solved, the dead pixel can be solved by local automatic fine-tuning of the design. For example, if there are 1000 dead pixels at the beginning, a considerable number of them may have been solved in the first step of local mask repair, and only a small number of dead pixels will go into the next step of local fine-tuning design.
According to the lithography ** feedback local automatic fine-tuning of the design layout, the changes to the entire design are minimal, and the function of the chip design itself will not be affected, but it can have a very positive help to the actual lithography. As shown in the figure below, 0The 2 nm design is automatically fine-tuned with remarkable results:
The following test example is based on a 4000um * 4500um complete RISC-V chip M2 layer at the 28nm node, and it can be seen that the number of dead pixels has been significantly reduced through the continuous improvement of Pangen DFO.
OPC plays an extremely key strategic pivotal role in the semiconductor industry chain, and fabs that do not have all the advanced nodes of OPC will lose the ability to transform chip designs into chip products, but the intractable bad pixels are like a few dark clouds in the clear sky, restricting the OPC recipe to play a more universal role, thereby affecting the production efficiency and yield of the fab. Based on the existing technical elements of Dongfang Jingyuan, Pangen DFO innovatively integrates local mask repair and local design fine-tuning progressively, continuously checks and fills in the gaps, resolves the stubborn bad points of OPC recipes, and provides more help for wafer fabs to improve yield more efficiently