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Over the past few decades, most of the advances, features, and innovations in semiconductors have occurred on the front end. This technological advancement, accompanied by increasingly complex designs and smaller geometries, is now peaking at the 3nm process node. But recently, achieving Moore's Law has become more challenging and costly, and the cost of building a 5nm chip is currently higher than the cost of building a 10nm and 7nm chip combined.
As the benefits of scaling with each new node continue to diminish, chipmakers are returning to the concept of nearly a decade ago: instead of making chips on a single piece of silicon, they combine individual functional chips, also known as "chiplets," which could be the next frontier in enabling Moore's Law and large-scale advanced manufacturing.
The top-level architecture involved in chiplet design
As mentioned earlier, manufacturing chips on a monolithic piece of silicon (often referred to as a system-on-chip or SoC) has led to a spike in costs. One way to achieve the same level of performance at a fraction of the cost is to combine chipsets with different features. There are three main architectural designs for compiling chiplets:
Fan-out: Fan-out utilizes DICE and redistribution layers to combine different chiplets. Fan-out isn't as fast or energy-efficient as other architecture systems, but it's easier to test and therefore faster to market.
2.5d：2.The 5D packaging method uses an interposer layer for stacked chiplet-to-chip communication, enabling higher communication rates. It can be paired with stacked memory modules to create high-performance modules. However, compared to other methods, 2The interposer layer of the 5D architecture is expensive.
3D: 3D vs. 2The general idea of 5D is the same, but it involves stacking logic on top of logic chiplets using through-silicon vias (TSVs) to produce the highest performing chip design.
Why companies are betting on chiplets
Companies such as AMD or Intel have been designing their own chiplets and interconnects for some time, albeit mostly through proprietary components and designs. Now, other semiconductor companies, such as NVIDIA, are also exploring chiplets due to the diminishing power and performance benefits that come with transitioning to new nodes, as well as the increasing complexity and cost of scaling.
Countries seeking to strengthen domestic manufacturing have not gone unnoticed this shift. The U.S. CHIPS and Science Act approved $2.5 billion last year for advanced packaging R&D projects, while China offers tax breaks and incentives for similar investments.
In fact, as requirements become more complex, advanced packaging appears to be a cost-effective way to combine chips while reducing RC latency. Chiplets also make it easier to develop complex systems that can be customized more quickly, while sourcing chips from multiple vendors, lowering barriers to entry and reducing the risk of disruptions.
In addition, chiplets can help the industry better address the ongoing thermal issues in advanced architectures. This, in turn, leads to improved reliability compared to traditional SoCs.
Chiplets still face challenges
As mentioned earlier, the concept of chiplets is not new, but applying it to modern chips is much more complex than the multi-chip modules of the past. This is one of the reasons why foundries and integrated device manufacturers are building their own ecosystems.
However, it will be much more difficult to create a commercial chiplet marketplace where chiplets from multiple vendors are developed according to agreed standards so that they are compatible with each other and truly plug-and-play. This work requires industry-wide collaboration and can take a decade to achieve an industry-wide breakthrough. Recently, large semiconductor manufacturers formed an alliance called General Chiplet Interconnect Express (UCIE), which can serve as the basis for the future state of multi-vendors.
To realize the potential of chiplets as the next frontier of semiconductor innovation, procurement, manufacturing, and packaging must be done in a standardized, repeatable, and scalable manner.
Chiplets: Blazing the trail to an intelligent world
In an era where manufacturing advanced nodes and implementing Moore's Law are becoming increasingly complex and costly, chiplets appear to be a viable way to gain design flexibility, reduce development time and costs, and reduce power consumption. But doing so will require a concerted effort, including reimagining the needs of the semiconductor ecosystem to enable industry-wide interoperability and integration.
Chiplets have all the ingredients to further advance chip performance. Investments from key industry players, ** incentive programs (e.g., CHIPS Act, EU CHIPS Act, etc.), and ecosystem partnerships can all work together to make chiplets a way to gain industry-wide buy-in. The implications are enormous: chiplets are bound to solve long-standing industry challenges, such as increased costs and outages, making devices smarter than ever.
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