(Report produced by Author: Hua An**, Zhang Fan, Tu Yueting).
Advanced Packaging: Efficient Integration, Reduced Costs
Advanced packaging generally refers to the packaging technology that integrates different systems into the same package to achieve more efficient system efficiency, which is a concept derived from the advanced wafer manufacturing process, in other words, as long as the packaging technology can improve the overall performance of the chip (including transmission speed, computing speed, etc.), it can be regarded as advanced packaging. High-density chip integration, miniaturization of volume, and lower cost can be achieved relatively easily through advanced packaging. Advanced packaging plays a more important role in improving chip integration, shortening chip spacing, speeding up the electrical connection between chips, and optimizing performance. It is becoming an important guarantee for the continuous improvement of system performance, and to meet the needs of "light, thin, short, small" and system integration. The extension of Moore's Law is subject to multiple pressures such as physical limits and huge capital investment, and there is an urgent need to promote technological progress in a different way. According to IBS statistics, after reaching the 28nm process node, if the process node continues to be reduced, the manufacturing cost per million gate transistors will rise instead of falling. Advanced packaging sits between wafer fabrication ("front-end") and chip packaging and test ("back-end"), known as the "middle end", and includes process technologies such as rewiring (RDL), bumping, and through-silicon via (TSV), which involve process steps such as lithography, development, etching, and stripping similar to wafer fabrication.
Catalysis for downstream application scenarios of advanced packaging
With the rapid development of cutting-edge technologies such as 5G, Internet of Things, high-performance computing, intelligent driving, and AR VR, the demand for high-end chips continues to grow. A large number of applications of these high-end chips rely on advanced packaging technology, in this context, the growth of advanced packaging is significantly better than that of traditional packaging, and the proportion of advanced packaging in the entire semiconductor packaging and testing market will continue to rise. In the long run, with the continuous upgrading of terminal applications and the improvement of chip packaging performance requirements, advanced packaging will also usher in a broad incremental space in the fields of AI, HPC, data center, CIS, and MEMS sensors.
Chinese mainland manufacturers are actively deploying advanced packaging
In March 2022, the UCIE Alliance, led by Intel, AMD, TSMC and other international manufacturers, was established, which defines the interconnection between chiplets in the package to achieve universal interconnection of chiplets at the package level and an open chiplet ecosystem. At the same time, leading domestic technology companies such as Huawei are also deploying chiplet advanced packaging technology.
Advanced packaging technology and product development complement each other
Advanced packaging technology and product design are mutually reinforcing, and general-purpose technological advancements drive product development. Advanced packaging to reduce the size, systematic integration, improve the number of IO, improve the heat dissipation performance as the main axis of development, can include single chip and multi-chip, flip package and wafer-level packaging are widely used, and with the technical ability of interconnection technology (TSV, BUMP, etc.) to further improve the integration of the system, internal and external packaging can be combined into different high-performance packaging products.
Key technology of advanced packaging - bump (bumping).
The Bumping process, also known as the bump process (flip second step), is a key step in the WLP (Wafer Level Packaging Process) process. Wafer bumps are essential for flip chip or board-level semiconductor packaging. Bumping is an advanced wafer-level process technology that forms "bumps" or "balls" of solder on a wafer in the form of the entire wafer before the wafer is cut into individual chips. These "bumps" can consist of eutectic, lead-free, high-lead materials, or copper pillars on a wafer and are the basic interconnect components that interconnect the chip and substrate together to form a single package. These bumps not only provide a connection path between the chip and the substrate, but also play an important role in the electrical, mechanical, and thermal performance of flip chip packages.
Bonding method
Chip bonding technology plays an important role in semiconductor manufacturing, providing a reliable electrical and mechanical connection between components, allowing integrated circuits to communicate with other parts of the system. The bonding form is mainly divided into wire bonding and bump bonding, bonding time can be divided into permanent bonding and temporary bonding, from the interface material can be divided into glue bonding with an intermediate layer, eutectic bonding, metal hot pressing bonding, fusion bonding without intermediate layer and anodic bonding.
Key technology for advanced packaging - rewiring layer (RDL).
The RDL (RedistributionLayer) rewiring layer plays the role of electrical extension and interconnection of the XY plane. In chip design and manufacturing, IOPad is generally distributed around the edge or periphery of the chip: IOPAD is a chip pin processing module, which can process the signal of the chip pin and send it to the chip pin, and can process the output signal inside the chip to the chip pin. This is convenient for the BondWire process, but more difficult for the Flipchip. Therefore, RDL is particularly critical: depositing the metal layer and the corresponding dielectric layer on the surface of the wafer and forming a metal routing, re-arranging the IO port to a new, more space-occupying area, and forming a map array arrangement.
Key technologies for advanced packaging - wafer-level packaging (fan-in and fan-out packaging).
Fan-out package, fan-in package. The fan-in packaging process is roughly described as the packaging and testing of a whole wafer chip, which is then cut into a single chip with the same size as the chip. Fan-out packaging generally refers to a package that does not require a substrate in the case of wafer-level panel-level packaging, such as FOWLP FOPLP, in a different package area than die. As the number of IOs increases, fan-out packages are derived when the chip size cannot accommodate all of them. Fan-out packaging is based on recombinant technology, after the chip is cut, the chip is re-embedded into the recombinant carrier board (8-inch, 12-inch wafercarrier or 600mmx580mm and other large-size panels), and the packaging and testing are carried out according to the steps similar to the fan-in packaging process, and then the recombinant carrier board is cut into a single chip, and the area outside the chip is the fan-out area, allowing the ball to be placed outside the chip area.
The biggest difference between fan-in package and fan-out package is RDL wiring, fan-in and fan-out refer to whether the bump BUMP exceeds the area of the die die In the fan-in package, RDL is routed inward, while in the fan-out package, RDL can be routed both inward and outward, so the fan-out package can achieve more IO.
5D package product - Codos
2.5DIC integration technology integrates logic computing and HBM chips by mounting logic computing (Logic) and HBM (High Bandwidth Memory) on a silicon interposer, and then placing them directly on the package substrate. The TSV RDL interposer is suitable for ultra-fine pitch, high I-O, high-performance, and high-density semiconductor IC applications.
Logic and HBM are first bonded side-by-side on a silicon interposer to form a chip-on-wafer (COW) with fine pitch and high-density interconnect wiring between devices. Each HBM consists of a DRAM with micro-bumps and a logic base with a pass-through TSV. Through-silicon vias (TSVs) are 2Features for 5D and 3D advanced packaging. TSVs are electrical connection paths, which are short vertical posts that pass through silicon wafers or chips that enable smaller package sizes and denser interconnects, improve electrical performance by shortening electrical transmission distances, and enable stacking of multiple chips used in products such as HBM. Finally, the assembly of the TSV interposer with large bumps is completed on the package substrate.
3D package products - HBM
HBM (High Bandwidth Memory) is a type of DRAM with extremely high bandwidth (data transfer rate). The input and output circuits (IO: input output) that connect memory and processors and exchange signals are called buses. The number of data signals passing through this bus per second is called the bandwidth, and the higher the bandwidth value, the faster the data processing speed. The bandwidth is determined by the transmission speed of one signal line x the number of buses.
HBM is able to achieve high transmission speeds and a large number of buses thanks to its high-density cabling with TSVs (through-silicon vias) and vertical memory stacking. It enables higher routing densities and shorter routing distances, reduced signal propagation delays, and higher operating frequencies compared to conventional wire bonding connections. In addition, by using a three-dimensional structure, a logic layer can be placed and connected under the memory chip to control memory operation and improve the efficiency of data transmission. HBMs do not exist in a single package, but in a multi-chip package combined with a host processor.
The growth rate of packaging equipment is on the rise, and the localization rate is expected to be further improved
Capital expenditure upward + advanced packaging, packaging equipment growth upward. SEMI **Semiconductor packaging equipment sales are expected to decline 31% to $4 billion in 2023, followed by 24% 2025 packaging equipment sales to $6 billion in 2025 as capex and advanced packaging advances. The localization rate of packaging equipment needs to be further improved, and advanced packaging is a big opportunity. According to the statistics of China International Bidding Network, the localization rate of packaging and testing equipment as a whole does not exceed 5%, which is lower than the localization rate of 10%-15% of process equipment as a whole. With the continuous advancement of advanced packaging, it will drive the localization of the original packaging equipment and new front-end equipment in the packaging process.
Added mid-to-front-end equipment - lithography machine
In advanced packaging, lithography machines are mainly used in: flipchip (FC) bump making, redistribution layer (RDL.).TSV in 5D 3D package, Copperpillar, etc. Unlike in front-end manufacturing, which is used for device molding, it is mainly used for metal electrode contact in advanced packaging. In addition, lithography machines are basically used in the wet process of advanced packaging and wet processing. TSV perforation realizes vertical interconnection between stacked chips, and drilling requires the cooperation of lithography and etchingOn flip BUMP, the bump is plated at a specific position on the chip, and photolithography is also required to hit the position of the bump ballIn RDL graphics transfer and reconnection, the pattern is passed through the reticle and then the lithography machine ** the pattern is punched onto the chip surface.
The original back-end equipment - die bonding machine
Diebonder, also known as placement machine, is the most critical and core equipment in the dieattach process of packaging and testing. The chip is grabbed from the cut wafer and placed on the dieflag corresponding to the substrate, and the chip is bonded to the substrate with silver glue (epoxy). The placement machine can place components at high speed and high accuracy, and realize key steps such as positioning, alignment, flip mounting, and continuous mounting.
This article is for informational purposes only and does not represent any investment advice from us. To use the information, please refer to the original report. ）
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