Research on the wire bonding process of the silver sintering process of the IGBT module

Mondo Culture Updated on 2024-01-30

IGBT module silver sintering process wire bonding process research.

Zhang Haoliang, Fang Jie, Xu Ninghua.

Zhuzhou CRRC Times Semiconductor *** State Key Laboratory of New Power Semiconductor Devices).

Abstract:The silver sintering process and copper wire bonding process applied to IGBT module packaging are mainly studied, and the process parameters of silver sintering and copper wire bonding are verified and optimized according to a series of quality characterization and evaluation methods, the influence of liner coating on the interface strength of sintered layer and copper wire bonding is analyzed, and finally the surge capacity and power cycle life test of the trial module are carried out. The results show that, compared with ordinary modules, the surge capacity and power cycle life of modules equipped with silver sintering and copper wire bonding technology are greatly improved, and there is no obvious degradation of the interface between silver sintering and copper wire bonding.

0 Introduction. In the fields of automobiles and new energy devices, the increase in the operating temperature and power density of power device modules has higher requirements for the reliability of module packaging interconnection. As the chip's capabilities increase, the silicon device may reach an operating junction temperature of 175. The traditional chip connection process is solder soldering, and the commonly used SNAGCU and SNSB solder are difficult to ensure the reliability of the module at higher operating temperaturesSecondly, the aluminum wire bonding point on the front of the chip has always been a shortcoming of the module's long-term reliability, and the aluminum wire bonding point will fatigue degradation when the module is subjected to periodic stress. Lead-free solders have a low melting point (210 240) and cannot be used for bond point strengthening with conventional PI adhesive coatings. Therefore, it is necessary to ensure that the modules can operate stably at high temperatures, but also to be able to ensure high reliability under cyclic "thermal-mechanical" stresses, and to develop interconnect processes that can replace traditional soldering and aluminum wire bonding points.

Silver sintering materials have higher thermal conductivity, electrical conductivity, mechanical strength, and a melting point close to that of pure silver, and the silver sintering process has quickly become one of the most promising interconnect technologies. Copper wire bonding points are a good alternative to aluminum wire bonding points, in addition to providing higher bond strength, copper wire also has a higher flow capacity than aluminum wire. However, there is still considerable difficulty in the process implementation, because the copper wire material is hard, and the front side of the chip must be made of thick copper metal to be compatible with copper wire bonding, which leads to the warping of the thin wafer after metallization, bringing new process problems.

This article discusses a high-reliability interconnect technology that combines silver sintering and copper wire bonding technology, known as DTS (Die Top System) technology. Literature studies have shown that this interconnect technology can significantly improve the power cycling capability of the module.

1. Test structure and process flow.

The test structure is shown in Figure 1(a), where the interconnect is achieved using a silver sintering process between the chip and the liner, with a piece of copper foil sintered on the front side of the chip as a buffer layer and copper wire bonding on the copper foil. Because the chip needs to be sintered on both sides, the front side also needs to be metallized. The basic process flow is shown in Figure 1(b), where the silver film is transferred to the back of the chip, followed by "chip-lining" sintering, and finally copper wire bonding on the copper foil.

2 Testing and analysis.

The sintering process of large-area silicon-based chips is studied with a chip size of 122 mm×12.2 mm with Ni AU plating on both sides. The chips are sintered onto a direct bonding copper (DBC) liner, and the surface metallization conditions of the liner are electroless nickel immersion gold (ENIG), AG, and CU. According to the process characteristics of silver sintering, it can usually be divided into pressure sintering and pressure sinteringDepending on the particle size of the sintered material used, silver paste is also divided into micro-silver, nano-silver, micro-nano mixed materials, and other additive silver pastes. In this paper, the nano-silver pressure sintering process is used, and the items verified by the sintering process mainly include sintering temperature, pressure and time, and the parameters are shown in Table 1.

In order to observe the bonding of the sintered interface, the sintered interface was analyzed using ultrasonic scanning, and then the microscopic morphology of the interface was observed, and the pores of the sintered layer were analyzed. The samples were cut and polished using epoxy mounting, the microstructure of the cross-section of the specimen was observed using optical microscope and scanning electron microscope (SEM), the composition of the interfacial diffusion layer was analyzed by energy dispersive spectrometer (EDS), and finally the images were processed and the pore distribution of the sintered layer was analyzed.

Use a diameter of 0The 375 mm copper wire was studied for the bonding process, including the main process parameters such as bonding pressure, ultrasonic energy and bonding time. The copper wire bonding process parameter curve mainly includes three stages, namely the initial contact, parameter rise and level holding stage. The process parameters of copper wire bonding at different stages were analyzed, and the thrust test was used as one of the evaluation indicators to characterize the shear strength of the bonding point, and then the samples were prepared and the bonding interface was observed using SEM to evaluate the bondingFinally, the module-level power cycling test was carried out under the condition of δt=100, and the conventional package module was simultaneously tested as a comparison objectAfter the failure of the module, the test life was compared, and the degradation of the silver sintered and copper wire bonding interfaces was analyzed compared to the pre-test period.

2.1 Silver sintering process validation and optimization.

Ultrasonic scan images of sintered layers on different coating liners under the same sintering conditions are shown in Figure 2. As can be seen from Figure 2, the ultrasonic scan results are similar at the interface of Au and AG plating, and there is no delamination and voiding at the sintered interface, but during the sintering process, the copper layer at the edge of the bare copper liner will oxidize at high temperatures, and the oxide layer hinders the diffusion between the sintered silver particles and the copper clad layer, and the interface is delaminated, and the image shows poor sintering at the edge of the chip.

Under the conditions of Niau plating and AG metallization of the liners, the silver sintering process is less demanding on atmospheric conditions. At different pressure levels, the porosity of the chips will be significantly different as can be seen from the light mirror and SEM images of the metallographic section (as shown in Figure 3). At higher pressure levels, the porosity inside the sintered layer effectively decreases, and the obvious porosity cannot be observed from the light microscope image, and under the appropriate process parameters, it can be seen that the boundary is difficult to observe after the atoms of the sintered silver and the liner coating diffuse each other.

In the sintering process, the sintering temperature and sintering pressure are the most important reaction drivers, and the sintering time is to ensure that the reaction takes place completely. The main driving force for the sintering reaction is the reduction of total surface energy, and there are two main reaction directions to achieve this result, namely densification and grain coarsening. In the early stages of the sintering reaction, atomic diffusion and grain boundary diffusion are the main reaction mechanisms, which are manifested by the merging of silver particles, the appearance and growth of sintering necks, as shown in Figure 4(a). In the middle and late stages of the reaction, bulk diffusion and grain coarsening became the dominant mechanisms of the reaction, which was mainly manifested by the continuous growth and merging of grains, and the number of sintered pores gradually decreased. As shown in Figure 4(b), in the densification-dominated tissue, there are more pores and smaller sizes;When grain coarsening dominates the reaction, it transitions to the topography shown in Figure 4(c), with larger pore sizes and co-grain growth. The trend of the thickness of the sintered layer over time at different times and temperatures under the same pressure conditions is shown in Figure 5. As can be seen from Figure 5, the densification rate of the sintered layer increases as the sintering temperature increases, and the densification rate of the sintered layer decreases rapidly after a sintering time of 5 min at 250 minutes.

2.2 Copper wire bonding process.

Compared with aluminum wire bonding, copper wire has a higher hardness, and the bonding process requires more pressure and energy, and there are certain requirements for the coating and substrate. Although the front of the chip is sintered with a buffer copper layer, the total thickness of the "copper layer + sintered layer" is still thin compared to the diameter of the copper wire, so too high bonding parameters can still cause the chip to be damaged and fail. Copper wire bonding was compared using liners with different coatings under the same process parameters, and shear strength was used as a characterization metric, as shown in Figure 6. The bonding strength of the copper wire of the silver-plated liner is slightly lower than that of the bare copper liner, because the thickness of the silver-plated layer is thinner, and the copper wire can destroy the copper clad between the coating and the substrate to form a direct connection, but this process will still consume part of the ultrasonic energy, and the thrust strength of the bonding point on the Niau plated liner has poor convergence, with a strength of 20 40 N, which is much lower than that of the bare copper liner, which is mainly due to the difficulty of the Cu and Ni atoms to form solution strengthening under the copper wire bonding process, and the interface bonding is poor. As shown in Figure 7, there is no good diffusion bond at the NI AU coating interface, and the continuous coating breaks during the bonding process, and the instability of the interface connection leads to large fluctuations in bond strengthThe copper wires bonded on the surface of bare copper belong to homogeneous metal bonding, and the interface diffusion is good, and no delamination and cracks are found.

2.3. Increase the extreme capability of the chip.

Figure 8 illustrates the surge capability of the FRD chip. After sintering the copper sheet and bonding copper wire on the front of the chip, the surge capability of the FRD has been significantly improved, and compared to the conventional "soldering + aluminum wire" bonding module, the surge capability of the prototype module chip has been greatly improved. Due to the addition of a sintered layer and a buffer gasket on the front side of the chip, the current is effectively averaged, and when the chip current reaches the surge limit, neither the front sintered layer nor the copper wire bonding point is damaged. Compared with the conventional module, the main failure mode of the surge failure of the trial module changes from the common chip emitter explosion to the field loop termination region failure.

2.4 Improvement of the power cycle life capability of the module.

Figure 9 shows the turn-on voltage drop curve of the power cycle life test, and the condition of the power cycle life test is δt=100. As can be seen in Figure 9, the cycle life of the test sample has been increased several times. The failure mode of the conventional module is the desorption of the aluminum wire bonding point on the front of the chip, resulting in the failure of the module interconnect, while the test module does not have electrical performance failure after a long power cycle test.

Analysis of the failed module shows that although the strength of the copper wire bonding points has degraded somewhat, it is still within the allowable range, while the aluminum metallization located at the edge of the chip shows signs of degradation due to the high cyclic stress. In the interconnect interface, signs of microcrack initiation are visible within the aluminum metallization layer on the front of the chip, with dimples and micropores appearing inside, as shown in Figure 10. As can be seen from Figure 10, the sintered interface is well bonded and there are no obvious cracks and delaminations. Therefore, when subjected to cyclic stress, the metallization layer on the front of the chip itself may become a potential failure risk point, which may gradually develop into a penetrating crack, leading to the eventual failure of the device.

3 Conclusion. In the sintering process, with the increase of sintering time, the thickness of the sintered layer gradually decreases at different temperatures, and the shrinkage speed of the sintered structure gradually accelerates with the increase of temperature, and the increase of pressure can effectively reduce the porosity of the sintered tissue. In the silver sintering process, the sintering effect of the Au and AG plating interfaces of the liner is similar, and both are better than those of the bare copper liner. Both the substrate and the plating conditions of the liner have a certain influence on the copper wire bonding process. Bare copper liners are stronger because they are homogeneous metal bonds with copper wires, while NI AU plating has cracks at the bond interface and has poor strength stability.

Generally speaking, compared with conventional packaging modules, chip double-sided silver sintering and copper wire bonding technology can significantly improve the fatigue life of the module, but the high material cost and additional process of this technology also lead to certain limitations in its application, and it is expected to have a good application prospect in the wide bandgap power devices of the silicon carbide series.

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