**: The content was compiled from semiwiki by Semiconductor Industry Watch (ID: icbank), thank you.
In yesterday's article "Next-Generation Transistors, Wafer Big Three", we talked about CFETS and TSMC's investment in them. Today, more details about the TSMC CFETT were reported by SemiWiki.
As mentioned in yesterday's article, TSMC published a belated ** this year titled: Complementary Fielet-Effect Transistor (CFET) Demonstration AD 48nm Gate Pitch for Future Logic Technology Scaling 。CFETs are a CMOS process in which transistors are stacked vertically rather than in the same plane as all previous logic processes: planar, FinFET, nanochip field-effect transistors (NSFETs, also known as ring gates or GAAs).
This ** was written by about 50 different authors, and I won't list them all, published by Sandy Liao. He said it was "belated news" because it was recent work.
It is speculated that TSMC will have a CFET process in the future, but this article describes early research on manufacturability. The process stacks n transistors on top of the p transistors. During the Q&A, Sandy was asked what motivated her for making this decision. It's not set in stone and may change in the future, she says, but putting PMOS at the bottom makes it easier to handle stress. TSMC refers to this as a monolithic CFET, or MCFET.
CFETs can reduce the area by 1., she said5x to 2x. There is still room for some vertical routing, so it is often not possible to get the expected 2x performance by stacking transistors. Previous studies of CFET fabrication have used a wide gate pitch, but have not succeeded in controlling the gate pitch to around 50nm. As a result, TSMC's study is the first to use 48nm gate spacing, which Sandy said is "relevant to industry-level advanced node scaling."
To achieve this, intermediate dielectric isolation, internal isolators, and NP source-drain isolation are required. This process provides a solid foundation for future advancements in MCFETs, which will require further innovation and additional architectural capabilities.
Here's a TEM demo of an MCFET. As I've already said, the NFET is at the top and the PFET is at the bottom. Both types of transistors have channels surrounded by a single metal gate.
Sandy said she would provide some details of the manufacturing process, "but not too much." It's a 20-step process, but obviously there are many sub-steps within each step. Currently, the process is expensive to manufacture, and she says engineers will solve the problem in a timely manner, so the process will have value. Here are the 20 steps.
By introducing intermediate dielectric isolation, internal sidewalls, and NP source-drain isolation, the vertically stacked transistors have a survivability rate of more than 90% and have high on-state current and low leakage. There are six orders of magnitude ion ioff current ratio.
In Sandy's speech, she came to the following conclusions:
This is just the beginning, and there is still a long way to go. But the situation with high-volume transistors will not get worse than this. We need to strive to generate true yield circuits with better process characteristics.
This is just a study that paves the way for a practical process architecture that can drive future advancements in logic technologies, scaling, and PPAC.
TSMC's future R&D plans
At last year's VLSI Technology & Circuits Symposium, Dr. YJ Mii, TSMC's Senior Vice President of R&D, delivered a presentation titled "Semiconductor Innovations, from Device to System." The presentation provides insight into TSMC's future R&D plans that go beyond the current roadmap. The challenges associated with the technology being studied were also highlighted. This article summarizes Dr. Mii's excellent presentation.
Dr. Mii began with a review of future end-market growth and emphasized the need for continued improvement in high-performance computing throughput and a focus on energy efficiency. For HPC needs, he shares a "digital data boom"**, as shown in the figure below. For example, a "smart" factory expects to collect, monitor, and analyze 1 petabyte of data per day.
He further noted that the role of machine Xi (training and inference) in supporting these applications is also expected to expand, placing further demands on HPC throughput. Dr. MII commented that these HPC requirements will continue to drive R&D efforts to increase logic density in semiconductor process roadmaps and advanced (heterogeneous) packaging technologies.
The chart below illustrates TSMC's relentless focus on power efficiency.
The architecture shown illustrates not only how ubiquitous 5G (and soon, 6G) will be in the devices we use, but also the operation of the "edge data center". As with HPC applications, the impact of machine learning Xi algorithms will be everywhere, requiring a focus on power efficiency.
Recent technological innovations
Before introducing some of TSMC's R&D projects, Dr. Mii briefly summarized recent semiconductor process technology innovations.
EUV lithography is introduced at node N7+.
TSMC said that TSMC's N7+ technology, which began mass production in the second quarter of 2019, is the first EUV process to bring a customer's product to market in large quantities. The N7+ process with EUV technology builds on TSMC's successful 7nm node, paving the way for 6nm and more advanced technologies. Among them, TSMC FAB 15 is the production base of N7+ EUV.
They further noted that the N7+ mass production is one of the fastest ever in FAB 15. Its yield is similar to that of the original N7 process, which has been in mass production for more than a year. At the time of the introduction of EUV in the N7+, TSMC's EUV tooling had reached production maturity and tool availability had reached the target goal of high-volume production, with an output power of more than 250 watts for daily operations.
According to TSMC at an earlier technical conference, they have 55% of the installed EUV lithography systems in the world. They further noted that the company will have ASML's next version of the state-of-the-art chip manufacturing tool, High-NA EUV, in 2024.
Today, the state-of-the-art chips are manufactured in a 5 4nm process, using the Twinscan NXE:3400C (and similar) system of EUV lithography ASML, which has 033 of numerical aperture (NA) optics that provide 13 nm resolution. This resolution is good enough for a single-mode approach at the 7 nm 6 nm node (spacing 36 nm to 38 nm) and the 5nm node (spacing 30 nm to 32 nm). But with pitches below 30 nm (beyond the 5 nm node), 13 nm resolution may require dual lithography**, which will be used in the coming years.
So for the post-3nm node, ASML and its partners are working on a new EUV tool – the Twinscan EXE: 5000 series – with 0A 55 nA (high-na) lens capable of 8nm resolution and is expected to avoid the use of multiple patterns at 3 nm and above. The new High-NA scanners are still in development, and they are expected to be very complex, very large, and extremely expensive – costing more than $400 million each. High numerical aperture requires not only new optics, but also new light sources, and even new fab buildings to accommodate larger machines, which will require significant investment.
TSMC will introduce the High-NA EUV scanner in 2024 to develop the relevant infrastructure and patterning solutions that customers need to drive innovation," said YJ Mii, TSMC Senior Vice President of R&D, at the TSMC Silicon Valley Technology Symposium. MII did not disclose when the device, a second-generation EUV lithography tool used to make smaller and faster chips, will be used for mass production. TSMC's rival Intel Corp. says it will put the machines into production by 2025 and that it will be the first to receive them.
Sige PFET channel for increased carrier mobility.
According to TSMC, silicon was the transistor channel material of choice for all CMOS technology generations until their 7nm node. But when it came to TSMC's 5nm technology, they pioneered SIGE as a p-type FinFET channel material for advanced logic production technology. TSMC emphasized that the company is also actively exploring alternative transistor channel materials to provide additional freedom in the design of high-performance and low-power devices. Silicon germanium and germanium are examples of TSMC's exploratory research work that has been widely published and in some cases recognized as a highlight of international conferences.
As you can see from the graph above, the high-mobility channel transistor improves the drive current (+18%). At first, it was commented that this could be a germanium channel (FIN), but given the lattice mismatch between GE and Si and the dislocations that will result, it seems more likely that we have a similar PMOS Sige channel, as TSMC's introduction above illustrates. Contains up to 40% GE compared to those used in the IBM Alliance's planar gate-first HKMG parts.
The analysis showed that in the planar version, the epi-sige was first grown and then removed in the NMOS region, in this case only 3-5 nm. If the active FIN height is about 55 nm and the total FIN height is about 120 nm, that's a different challenge, but given all of TSMC's work on nanosheet devices, it can now be assumed that they can do a very selective etching of Sige vs. Si. However, for TSMC, the bigger problem in the follow-up is that if this method is used, the Sige Fin will be tens of nanometers higher than the Si Fin, increasing the complexity of subsequent processing.
The correlation analysis further states that in order to keep the fin at the same level, I guess we can do etching of the n or p region and then do si or sige epitaxy plus cmp (or selective epitaxy?).), depending on the area etched;It doesn't seem to be simple either. And I think we'll do separate FIN definition etching for the SI and SIGE fins, which sounds confusing as well - maybe the FIN etching is now also an EUV implementation?
Design Technology Co-Optimization (DTCO).
Dr. Mii highlighted how process technology development has evolved to place a greater emphasis on DTCOs, where assessing the trade-off between process complexity and design improvement has become an integral part of process development. He highlighted the recently adopted active gate contact and single diffusion interruption process steps as examples. He adds, "DTCO's work is not limited to logic design – memory and analog circuitry are also key aspects of DTCO evaluation. ”
According to TSMC, co-optimization of design technology literally means that design and process technology seek integrated optimization to improve performance, power efficiency, transistor density, and cost, and often undergo major architectural innovations when supporting new process technologies, rather than providing the exact same structure as the previous generation of technology, only to be smaller.
They pointed out that the fruits of DTCO are by no means easy to obtain, the process R&D team and the design R&D team must work together at the beginning to carry out design technology co-optimization for the definition of the next generation of technology, the two teams must keep an open mind and explore the possibility of design innovation and process capabilities, many innovative ideas are proposed at this stage, some of which may be too positive to be realized by existing technologies, some ideas may initially seem to have great potential, but the results are not so practical, the purpose of design technology co-optimization is to define truly meaningful adjustments, beyond simple geometric miniatureto achieve the goal of improving performance, power consumption, and area.
After the parameter definition of the design technology co-optimization, the next step is to find the limit of the "process window", and define the scope boundary of the process to achieve the best performance, power consumption, and area through intensive back-and-forth interactive process adjustments, and still produce mass production with high yield.
To ensure that the performance, power, and area advantages brought by co-optimization of design technologies can be applied to customers' products, TSMC works with the electronic design automation partners of the Open Innovation Platform Alliance to use tools that accurately comply with the new process design principles, and take full advantage of the new technology optimizations to optimize designs and achieve the goals of performance, power, and area.
Regarding TSMC's views on DTCO, refer to the article "TSMC Official Popular Science: What is DTCO?".》
Nanosheets are introduced at 2 nm.
TSMC's N2 is an entirely new platform that makes extensive use of EUV lithography and introduces Gaafet (which TSMC calls nanosheet transistors) as well as backside power delivery. The new ring-gate transistor architecture has well-known advantages, such as greatly reduced leakage current (all four sides of the gate now surrounds the channel) and the ability to adjust the channel width to improve performance or reduce power consumption. As for the rear power rail, it is usually designed to provide better power delivery to the transistor, providing a solution to the problem of increased resistance in the back end (beol). New power delivery solutions are designed to improve transistor performance and reduce power consumption.
From a feature set perspective, TSMC's N2 looks like a very promising technology. As for the actual numbers, TSMC promises that N2 will allow chip designers to improve performance by 10 to 15 percent at the same power and number of transistors, or reduce power consumption by 25 to 30 percent at the same frequency and complexity, while increasing chip density by 1 compared to N3E nodes1 times more.
Compared to N3E, TSMC's N2 nodes deliver the same performance gains and power reductions that foundries' new nodes typically bring. But the so-called chip density increase (which should reflect the transistor density gain) is only slightly more than 10%, which is not particularly encouraging, especially considering that N3E already offers a slightly lower transistor density compared to regular N3.
Innovation in the future of semiconductor technology
In his presentation, Dr. Mii then presented several semiconductor technology R&D efforts for future application needs.
The first thing he talked about was CFET (Complementary FET).
After decades of planar FET device technology, FinFETs have also experienced a fairly long lifespan, from N16 N12 to N7 N6 to N5 N4 to N3 N3E. It will be interesting to see how the process nodes based on nanosheet devices evolve. From Dr. Mii's introduction, we can see that after nanosheets, TSMC is focusing on the introduction of CFET devices.
As shown in the figure below, the CFET process retains the benefits of gate-by-ring nanosheets, but fabricates PFET and NFET devices vertically. (In the diagram, the PFET is at the bottom and the NFET is at the top.) ）
In the cross-section of the inverter logic gate described above, the common gate input and common drain node of the two devices are highlighted. The diagram below expands on the process development challenges posed by CFET device stacking, specifically the need for high aspect ratio etching and associated metal trench filling to achieve the vertical connections highlighted above.
Now, different researchers studying CFET process development have been pursuing two paths: a "sequential" process in which the PFET and NFET devices are implemented using an upper thinned substrate for top device fabrication, which is bonded to the starting substrate with a dielectric layer in the middle after the bottom device is fabricated
A "monolithic" process in which a set of epitaxial layers is applied to all devices on the substrate. There are trade-offs between process complexity and thermal budgets, equipment performance optimization (using multiple substrate materials in a sequential process), and cost between the two approaches.
While Dr. Mii didn't specify, comments about High AR etching and metal filling suggest that TSMC's R&D focus is on monolithic CFET process technology.
For more information on CFET, please refer to the article "Transistors after 1nm, iMEC Includes CFETTs in the Roadmap".
Secondly, 2D transistor materials are another direction that TSMC is focusing on.
There are active studies evaluating "post-silicon" materials for FET channels. As shown below, 2D materials offer the potential to improve carrier mobility and subthreshold slope (with the potential for lower leakage current and lower VDD operation) as the gate length and channel body thickness of the device decrease.
One of the main challenges in 2D process development is to provide a low-contact resistance connection to the source-drain node of the device. Dr. MII shared previously published results from TSMC researchers, highlighting the evaluation of bismuth (BI) and antimony (SB) – a 5-fold reduction in RC compared to previously published work, as shown below.
In 2021, Taiwan University of China, TSMC and the Massachusetts Institute of Technology (MIT) jointly published a study that proposed for the first time that the use of semi-metallic bismuth (BI) as a contact electrode of a two-dimensional material can greatly reduce the resistance and increase the current, making its efficiency almost the same as that of silicon, which will help realize the challenge of 1nm semiconductors in the future.
In the study jointly published by National Taiwan University, TSMC and the Massachusetts Institute of Technology (MIT), the Massachusetts Institute of Technology team first found that electrodes with semi-metallic bismuth (BI) on two-dimensional materials can greatly reduce resistance and increase transmission current. Subsequently, TSMC's corporate research department optimized the bismuth (BI) deposition process, and the NTU team successfully reduced the element channel to nanometer size using helium-ion beam lithography, and finally obtained this breakthrough research result.
Professor Wu Zhiyi of the Department of Electrical Engineering and Institute of Optoelectronics at National Taiwan University further explained that after using bismuth as the key structure of the contact electrode, the performance of the 2D material crystal is not only comparable to that of silicon-based semiconductors, but also has the potential to be compatible with the current mainstream silicon-based process technology, which will help break through the limits of Moore's Law in the future. Although it is still in the research stage, this achievement can provide excellent conditions such as power saving and high speed for the next generation of chips, and it is expected to be used in the future to apply emerging technologies such as artificial intelligence, electric vehicles, and diseases**.
Third, the BEOL interconnect architecture.
The scaling of the back-end interconnect is challenged by the inefficient use of existing (mosaic: damascene) copper wires. The Cu diffusion barrier (e.g., Tan) and adhesion liner (e.g., TA) in the mosaic groove occupy the increased percentage of the proportionally scaled wire cross-section. The deposition grain size of Cu deposition is also limited, resulting in greater electron scattering and higher resistivity. The diagram below highlights TSMC's R&D efforts to introduce a new (subtractive-etched) BEOL technology.
With the Subtractive Metal process, new opportunities are introduced for fabricating dielectrics between wires – the diagram above illustrates the "air gap" cross-section within adjacent dielectrics.
Yu Zhenhua, TSMC's Distinguished Technology Academician and Vice President of R&D, previously said that TSMC's 3D Fabric platform has been established and has taken the lead in entering a new stage, which has evolved from heterogeneous integration and system integration to the current system miniaturization.
Yu Zhenhua mentioned that heterogeneous integration technology has become a new manifestation in the industry at TSMC from initiative to blossom, which will provide more value for semiconductors. It is believed that both the front-end process and the back-end process industry are happy to see such a development of semiconductors. TSMC has also observed that the current system scaling-like SoC has been further upgraded from the past in terms of performance, power consumption and area, to the pursuit of volume reduction.
However, there are also two major challenges in the development of related technologies, the first is cost control, in terms of cost control, because advanced packaging is micron level, but the current process has already entered nanometers, process integration needs to be improved if TSMC BEOL front-end process or traditional packaging equipment is cut, for example, the cost of copper process equipment is a challenge, control is not a problem, but the size of the wire width and time consumption are more cost problems.
The second is accuracy, Yu Zhenhua said, borrowing the BEOL front-end process, related material cost control and efficiency is a challenge, but if the traditional back-end equipment is used to do, there is a challenge of accuracy, both of which are expected to work together in the upstream and downstream of the industry, and SEMI will play the role of an intermediary to jointly promote.
For more information about BEOL, please refer to the article "Key Technologies of 1nm, IMEC Announces New Progress".
Finally, TSMC talked about 2D conductors.
The diagram above shows the cross-section of a 2D conductor layer and the resulting conductivity advantage compared to comparable copper wire thicknesses.
Dr. Mii did not elaborate on the specific material being evaluated. For example, there are a number of transition metal compounds that exhibit high carrier mobility in 2D crystal topologies, as well as the ability to stack these layers, which are influenced by Van der Waals Forces.
Finally, Dr. Mii concluded his presentation with the slides shown below. He said that future system design will leverage the following technologies:
Increase transistor density, e.g. for CFET devices (and DTCO-focused process development).
New interconnect materials;
Add integration of heterogeneous features in advanced packaging, including 2Chiplet and HBM stacks in 5D and 3D configurations;
New methods for system design zoning, physical implementation, and electrothermal analysis;
SemiWiki says it's an exciting time to enter the industry right now, both for designers and process engineers.