With the deepening of the concept of green energy, the development of electric vehicles has become the key direction of future development. The advantages of electric vehicles are zero or near-zero emissions, low environmental pollution, low cost of use, and simple maintenance. However, according to the current use status, the difficulty of restricting the development of electric vehicles lies in the charging problem, due to the defects of the distribution and design of charging piles, the endurance reliability of electric vehicles is affected, therefore, it is of great significance to study the optimal design of electric vehicle charging piles, and the core of the design of electric vehicle charging piles lies in the design of the control system, and the intelligent charging capacity of charging piles is improved through the design of embedded control systems for electric vehicle charging piles.
1.1. Description of the overall design of the embedded control system of the charging pile
To design an intelligent charging pile-in control system based on embedded technology, it is necessary to first describe the overall structure design and functional indicators of the intelligent charging pile system, and use the AD system of S3C2440 to design the channel synchronous sampling of the intelligent charging pile-in control system. The intelligent charging pile embedded control system mainly includes two parts: hardware design and software design, among which, the main control module is the core of the control system, and the signal detection module of the charging energy control for charging is mainly composed of three parts: charging signal access and power supply design. The hardware design of the system is AD circuit system, ARM main control circuit board, synchronous clock design, charging signal conditioning circuit, etc. Thus, the overall design of the module of the embedded control system of the intelligent charging pile is obtained.
Through the overall design architecture of the intelligent charging embedded control system, the functional index analysis of the system is carried out, and the voltage range of the chargeable control system is: + -220 V + 360 V, with a 16-bit fixed-point STM32 core, which can achieve continuous operation of 600 kHz, and the maximum sampling rate of the system is 250 kHz, which can be configured as a 4-way group combined cache system with low power consumption, supporting off-chip synchronous or asynchronous memory (including PC133 SDRAM) , the power consumption of the system in the regulated state is 140 mW (250 kHz, 5 V supply). In addition, the system has can20B interface, with 8 x 32-bit timer counters, supports PWM. According to the above overall design description and index analysis of the embedded control system of the intelligent charging pile, the modular design of the system is carried out. Here, the device selection of the system is carried out.
1.2. Device selection and establishment of embedded STM32 development environment
According to the above-mentioned design requirements and index analysis of the embedded control system of the charging pile, the modular design of the system is carried out, the system design adopts the ST ultra-low power ARM CortextM-Mo microcontroller as the main controller of the control system, and the software design of the system is based on the Linux2632 kernel as the platform, and the software development of the charging man-type control system is carried out with 8-bit and 16-bit microcontrollers, which can realize the advanced and complex functions of the intelligent charging pile on the economical user-end products. The development of embedded software systems usually uses a cross-compilation environment, that is, the development environment is installed on a desktop or server computer system, and the developed system runs on an embedded computer of other architectures. Assuming that ChanVector is the list of acquisition channels and FS is the sampling frequency, the program loading is executed from the external program memory at 0ff80h, and the program guide loading mode is executed from the off8h of the on-chip ROM to connect the target board of the embedded control system of the charging pile with a 232-port network cable and the host computer using a 232-port network cable, and the hardware connection of the intelligent charging control system development environment based on STM32 is adopted.
The Linux system is selected as the embedded operating system, the cygwin system is installed in the Windows system, the compiled files are transferred to the Windows system, and the intelligent charging human control application "simulates" a standard PC environment in the binary compiled by various compilers used in Linux** to achieve GCC compilation. The AD acquisition module of the charging humanoid control system is composed of two parts, which is the signal conditioning part and the other is the acquisition chip part. The data memory of the AD set module includes two 32 KB SRAM banks, and the AD acquisition chip is responsible for collecting the analog signal of the embedded control information of the intelligent charging pile and converting it into a digital signal, and transmitting it to the main control system for post-stage digital processing. The main control system is the core of the entire intelligent charging pile embedded human control system, which is designed by the embedded design method of STM32, and the user control panel is built with 4 channel group joint caches, and 8 32-bit timer counters are used for intelligent charging of electric vehicles. According to the embedded STM32 development environment established above, the modular design of the system is carried out.
2.1. Design part
According to the analysis of the above overall design model, the optimization design of the embedded control system of the intelligent charging pile is carried out, and the hardware modular design of the embedded control system of the intelligent charging pile is carried out based on the embedded technology, and the hardware circuit design of the system mainly includes the sensor module design of the intelligent charging pile, the RTC module circuit design (including the amplification circuit, the conditioning circuit, the filter circuit, etc.), the clock circuit design, the STM32 main control system module design, the reset circuit design and the display module design, etc., which are described as follows:
1) The sensor module of the embedded control system of the intelligent charging pile is mainly used for the sampling and detection of electric vehicle charging information and data, and the signal sensor is constructed through low-voltage reset and watchdog reset to detect the embedded control information of the intelligent charging pile, and the parallel peripheral interface ( PPI builds the sensor module of the intelligent charging pile embedded control system, which is in half-duplex form, supports 8 stereo PS channels of AD data sampling The interface mode of the sensor module of the intelligent charging control system is serial, and the connection with the embedded STM32 host adopts dual 16-bit current output type D A conversion, which can carry out the maximum output of 16-bit data, combined with AD DA The converter realizes the real-time acquisition of intelligent charging control information of electric vehicles, and according to the above analysis, the interface circuit of the sensor module of the intelligent charging pile embedded control system is obtained.
2) RTC module circuit design is to realize the amplification, filtering and detection of the embedded control information of the intelligent charging pile conditioning function, the use of S3C2440ARM9 chip to build the intelligent charging pile embedded control system of the signal conditioning LCD controller, due to the STM32 control timing is more complex, at the same time the oscillation signal generated inside the crystal oscillator will affect the sampling accuracy and control accuracy, in order to ensure the stable and reliable operation of the circuit of the embedded control system, the use of complete The RGB data signal output model is used to amplify, filter and detect the signal, and realize the interruption of the control clock, and according to the above analysis, the RTC module circuit designed in this paper is obtained.
3) The clock circuit design is the basis for processing digital information, and it is also the key module of the embedded control system of the intelligent charging pile.
4) The STM32 main control module is the core of the embedded control system of the entire intelligent charging pile, and the technical parameters of the main control module of the embedded human control system of the intelligent charging pile are given by using the embedded design technology.
According to the above design indicators, the S3C2440A ARM9 processor is used to form a core frequency of 20 MHz after 24 frequency doubling, the cross-compiler used to unify the control loading to ArmLinux-GEC, and the control and computing core realize the main control module design of the intelligent charging pile embedded control system through STM32, combined with embedded design technology, using S3C2440, running at 400MHz. NOR Flash is a 2M sequential control logic S that receives data detection and output feature display from the embedded control of the intelligent charging pile, and converts it into control logic pulses.
2.2. Software development and implementation
On the basis of the above-mentioned hardware design, the software development of the embedded control system of the intelligent charging pile based on STM32 is carried out. The development platform of this system software is ARM CortextM-MO, which supports Analog Devices' Blackfin series SHARC series and TigerSHARC series of human-style microprocessor control chips, and uses embedded system development technology to initialize the hardware circuits and modules of the embedded control system of intelligent charging piles 0 initialization, the output window will display the compilation link process, use the program written in C C++, realize the setting of the label or address breakpoint in the CAN synchronous serial port, and design the Linux kernel, system sequence shell and application sequence of the embedded control system of the intelligent charging pile in the embedded system.
System startup and remote control are achieved through process management of the location of the stack or memory. The Siulator and Emulator of VisualDSP+10 are used to determine the storage space required for variables and arrays, combined with the STM32 embedded processor for compiler or assembler program compilation, the GPIO is used to simulate the SPI rechargeable control information detector SCLK to give the clock signal, and the program of the test design is configured by configuring the operating mode of the PPI from the Douta serial interface, the signal polarity and the data width The GPIO pins are ordered as dmax x count gpio setpin ( process management gpf(0),1);
dma0_x_modify delay(5);dma0_y_modify_setpin(s3c2410_gpf(0)，0)；Through the tube driver configuration, the Sporto TCLKDIV is set to 4, that is, the serial port transmits the clock to 12MHz, and the convst module of the AD7656 is triggered under the humanoid system to realize the intelligent charging pile entry control.
Source: Electronic Measurement Technology.Original title: Design of embedded control system for intelligent charging pile based on STM32.
Authors: Zhang Xiaojun, Xie Huidi, Xu Jianrui, Xu Zhaoyang.