The manufacturing process of semiconductor components includes the front-end manufacturing process and the back-end packaging and testing process. The packaging and testing link is the bridge connecting the wafer to the components, which is located after the design of semiconductor components and before the end product, and belongs to the back-end process of semiconductor manufacturing.
The packaging process is the process of layout, fixing and connecting the chip on the substrate, and potting it with a plastic insulating medium to form an electronic product, with the purpose of protecting the chip from damage, ensuring the heat dissipation performance of the chip, and realizing the transmission of electrical energy and electrical signals to ensure the normal operation of the systemThe test process is to use professional equipment to test the function and performance of the product.
According to SEMI's statistics on the global semiconductor packaging equipment market, packaging and testing equipment accounts for about 15% of the overall market share of semiconductor equipment and belongs to core process equipment. With the continuous enrichment of downstream application scenarios and the continuous improvement of the requirements for the process technology of packaging and testing, semiconductor packaging and testing has gradually entered the core area of the industrial chain and has become one of the main pillars of extending Moore's Law.
In the packaging process, each link and process stage corresponds to a certain type of packaging equipment. Among them, LED chip packaging equipment mainly includes crystal expansion machine, die bonding machine, wire bonding machine, glue filling machine, light splitter, taping machine, etc. Semiconductor packaging equipment mainly includes thinning machines, cutting machines, die bonding machines, wire bonding machines, etc.
(1) LED packaging field
LED packaging is a key link in the LED industry chain. Through the packaging, it can provide electrical input, mechanical protection and heat dissipation channels for LED chips to achieve high-efficiency and high-quality light input. The main packaging processes in the LED field include die bonding, wire bonding, glue potting, light separation, and tapeing.
(2) Semiconductor packaging and testing field
Compared with the LED packaging field, packaging and testing in the semiconductor field generally starts from the wafer, and the wafer is cut into wafers through the thinning and dicing process to achieve the required thickness of the package. However, in the wafer stage, packaging and testing in the semiconductor field also requires the chip to be fixed on a specific carrier, and the wafer is connected to a specific carrier through a bonding wire to form a signal transmission channel that communicates with the outside world. Therefore, the packaging and testing in the semiconductor field also includes die bonding and wire bonding processes, and these processes have certain commonalities with the packaging in the LED field in terms of equipment and technology, and the main difference is in the processing accuracy, and the specific content of each process is as follows
(3) Classification of package interconnect technologies
Depending on the chip package interconnect technology, semiconductor package interconnect technology is mainly divided into wire bonding (for pin count 3-257), carrier tape automatic soldering (for pin count 12-600), and flip soldering (for pin count 6-16000).
1) Wire bonding
Wire bonding process: On the chip electrode (PAD) and bracket pins in a wire bonding package (lead), a reliable electrical connection is formed through ultrasonic hot pressure welding of the bond wireThe connection between the chip electrode and the gold wire is gold ball welding, and the connection between the bracket and the gold wire is a wedge-shaped fishtail connection.
At present, the main packaging technologies applicable to wire bonding interconnects are SIP, DIP, SOP, QFP, QFN, WB-BGA, and 3D 25D packaging, SIP, etc.
2) Automatic welding of carrier tape
Tape Automated Bonding (TAB) is an assembly technology that mounts and interconnects wafers onto flexible metallized polymer carrier tapes, and is an interconnection process for chip leadframes. The process flow of TAB is as follows: firstly, the conductor pattern of the component pins is made on the polymer, then the wafer is placed on it according to its bonding area, and then the bumps on the chip are soldered together with the solder joints on the carrier tape, and all the leads are bonded in batches through the thermoelectrode at one time, and finally the soldered chip is sealed and protected.
3) Flip welding
Flip soldering is to prefabricate bumps on the electrodes of the chip, and then connect the bumps to the corresponding electrode area of the substrate or lead frame. The integrated circuit chip is connected to the carrier or substrate with the active side facing down. The interconnection between the chip and the substrate is achieved by the bump structure on the chip and the bonding material on the substrate, which enables both mechanical and electrical interconnects. For high-density chips, flip soldering has a strong advantage in performance.
In general, the electrical properties of the carrier tape automatic and flip weld interconnects are better than those of wire bonding, but additional equipment is required. As a result, for chips with a small number of IO, automatic carrier tape and flip soldering result in higher product costs, and in 3D packaging, stacked chips cannot all be upside down on the package body, but can only be interconnected to the package body by wire bonding or TSV.
Based on the above reasons, wire bonding has always been the mainstream technology of chip interconnection, and it is an important means and method of implementation in chip electrical interconnection.
(4) Wire bonding is the core process of packaging and testing, which continues to evolve with the upgrading of materials and technologies
At present, more than 90% of chip interconnection packages rely on wire bonding technology to complete, and wire bonding will exist as the main interconnection technology in most chip packages for a long time in the future, and continue to be used in a large number of package types. From 2015 to 2021, the global wire bonding market size grew at a CAGR of 21%, maintaining steady growth.
The rest of the packages that do not apply wire bonding technology are mostly used in a small number of chip packaging links that require high integration and accuracy or have special properties, and the application scenarios are relatively limited. With the diversification of wire bonders and wire bonding materials in the future, combined with the application of new materials, new processes and new technologies, wire bonding will enter more packaging processes to meet the large demand for semiconductor packaging.
(5) Packaging application fields and corresponding packaging forms