**: The content comes from the Semiconductor Industry Watch (ID: icbank) synthesis, thank you.
In a world where tech giants dominate the process of technological evolution, Meta's embrace of RISC-V at the RISC-V Summit in the United States is significant. The company has revealed plans to implement RISC-V across a range of products. "We've identified RISC-V as the way we need to move forward with all of the products in our roadmap. This includes not only next-generation transcoders, but also next-generation inference accelerators and training chips. Prahlad Venkatapuram, senior director of engineering at Meta, said. This decision isn't just about keeping up with trends;This is a strategic move to address major challenges.
Meta emphasizes the need for acceleration for business-critical tasks, which cannot be met by traditional CPUs alone. The quest for power efficiency, performance, low latency, flexibility, and architectural resiliency is the driving force behind Meta's adoption of RISC-V. But this is where the plot gets more complicated – even after major customization, Meta found itself needing to get more out of its existing IP options. "There are very few products that seamlessly integrate custom instructions and resources into RTPs, simulators, software tools, and compilers," Venkatapuram explains. This brings us to the heart of the matter. Meta points to a key gap in the market: the scarcity of products that allow for the seamless integration of custom instructions into key software tools such as emulators and compilers. We couldn't agree more. In fact, this premise is the foundation of our custom computing products.
Meta's RISC-V journey, particularly in the area of transcoding with Scalable processors (MSVPs), provides a real-world demonstration of the success of RISC-V customization. By leveraging RISC-V, Meta has replaced a significant portion of its CPU with its custom processors, achieving significant efficiency gains.
Venkatapuram said that over the past four years, they have actively plotted to incorporate the RISC architecture, not only launching production hardware, but also laying the groundwork for future custom RISC-V chips with standardized RISC-based chips. control the system and make it scalable, so any IP element developed for any domain can be adapted and easily connected to the NOC.
In other words, Meta has a template to quickly put any new chip of this kind into production, which is a big deal for those looking for a large-scale RISC-V success story. All of this is happening in the midst of a shortage of high-end GPUs ** – and *is also reflected.
Venkatapuram said Meta chose RISC because of the need to accelerate all "business-critical tasks that we can't do on CPUs," as well as "power efficiency, performance, and absolute low latency on servers." He added that the flexibility to support different workloads and the resiliency of the architecture are also crucial.
Whenever we design or deploy, we want it to last 3-4 years, so it has to be resilient and programmable – we want the software to be responsible for how we use hardware resources. ”
He added that 64-bit addressing is critical, as are vector and simd capabilities in the kernel, emphasizing the need for deep customization. "It's clear that the RISC-V can do all of these things;It's open, there's strong support, there's multiple IP providers, and we've seen an ever-evolving ecosystem in the last 4-5 years. But in the end, customization is key.
Meta, the transcoding hardware built only on RISC-V, provides the context for the customization part. According to Venkatapuram, Meta's Scalable Processor (MSVP) was the starting point of Meta's journey to production RISC, which is now in production and handles 100% of all uploads across its Facebook, Messenger, and Instagram services. "We used to do this on the CPU, but now we've replaced 85%, so we're only using 15% of the CPU. ”
The real story, which should draw the attention of the processor world, is that Meta is skipping the ubiquitous GPUs and building AI inference and training chips on RISC-V. As we present here, the Facebook giant revealed some of this work in May, and the project has been going on since 2020.
Currently, the RISC-V AI processor is dedicated to accelerating the inference and training of recommendation models. The architecture is no stranger to the 8 8 processing element mesh, with each element hosting 2 RISC-V cores (one scalar, one vector) and one core for control. The scalar and vector cores are synchronized with the command processor, which is used in conjunction with the built-in pinning features developed by Meta.
Other than that, we don't know, but we'll ask for more insights, including the production volume of Meta's RISC-V architecture.
While all of these are promising, there are some challenges that are really hesitant, although they don't seem to dampen Venkataplam's optimism.
Despite the mass customization, Meta still needs more of its existing IP options. "There are very few products that seamlessly integrate custom instructions and resources into RTPs, simulators, software tools, and compilers," he explains. Another challenge was the lack of interoperability among the vendors, but he didn't provide in-depth details. Ultimately, the feeling is that the challenges are not insurmountable.
One of the most significant hurdles is support for matrix scaling, especially as Meta seeks to build more production AI workloads on RISC-V. He explained that matrix math is a key component of artificial intelligence, and while RISC-V has vector extensions, matrices do not have standard extensions. He cited the work being done in this area (many vendors, including stream computing and T-head SEMI), but ultimately, whatever they propose, should be standardized.
Venkatapuram began by emphasizing the importance of broader ecosystem support, from support for all major libraries and tools to the hardware ecosystem
Due to its open-standard nature, RISC-V has the potential to attract more third-party tool, software, peripheral providers, and not just proprietary ISAs, but this potential has not yet been fully realized. ”
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