Students, do you know what PCIe protocol is? PCIe protocol is the abbreviation of Peripheral Component Interconnect Express, which is a high-speed serial computer expansion bus standard, which is mainly used to connect various devices in computer systems, such as graphics cards, network cards, sound cards, etc. The PCIe protocol is based on the old PCI protocol, but it has many new features and advantages, let's take a look at them one by one.
First, the PCIe protocol uses point-to-point serial communication instead of a shared parallel bus like the PCI protocol. This means that each PCIe device has its own dedicated data channel and does not need to compete with other devices for bus resources and is not subject to interference from other devices. We can think of the PCIe protocol as a highway where each device has its own lane and can drive freely without traffic jams or crashes. The PCI protocol is like an ordinary road, where all the equipment has to be crowded together, which is easy to cause congestion or accidents.
Secondly, the PCIe protocol supports a variety of different channel numbers and rates, which can be flexibly configured and expanded according to different devices and needs. The number of channels refers to the number of data lanes per PCIe device, and each lane consists of two pairs of data lines, one pair for sending and one pair for receiving. Rate refers to the amount of data that each channel can transmit per second, and is expressed as GT S (GigaTransfer per Second). There are currently six versions of the PCIe protocol, starting with 10 to 60, the number of channels and rate are different for each version, as shown in the following table:
As can be seen from the table, the rate and bandwidth of the PCIe protocol increase with the edition, which provides greater data transfer capacity for high-performance devices. We can choose the appropriate number of channels and versions according to different devices, for example, the graphics card generally uses the number of channels of x16, the network card generally uses the number of channels of x1 or x4, and different devices can use different versions, such as PCIe 4A graphics card of 0 can be compared with PCIe 30 motherboards are compatible, but the rate will be reduced to PCIe 30 level.
Thirdly, the PCIe protocol adopts a multi-layer protocol structure, which can realize the effective transmission and configuration of data. The hierarchy of the PCIe protocol is somewhat similar to the protocol implementation of TCP IP, but the various layers of the PCIe protocol are implemented through hardware logic. The hierarchy of the PCIe protocol is shown in the following diagram:
As can be seen from the figure, the PCIe protocol consists of four layers, namely the application layer, the transaction layer, the data link layer, and the physical layer. Each level has its own function and role, let's briefly introduce it:
Application Layer: This is the highest layer that is responsible for handling requests for application and device drivers, as well as providing configuration and management capabilities. The data unit at the application layer is called the transaction layer packet (TLP), which is the basic transmission unit of the PCIe protocol, which contains information such as the destination address, data length, and data content.
Transaction layer: This is the second layer, which is responsible for encapsulating and decapsulating the TLP of the application layer, as well as performing functions such as flow control, error detection, and retransmission. The data unit of the transaction layer is called the data link layer packet (DLLP), which is the basic transmission unit of the data link layer, which contains information such as serial number, check digit, and type.
Data Link Layer: This is the third layer, which is responsible for encoding and decoding the DLLP of the transaction layer, as well as transmitting and receiving data, as well as acknowledging, retransmission, power management and other functions. The data unit of the data link layer is called the symbol, which is the basic transmission unit of the physical layer, which contains information such as data bits and control bits.
Physical Layer: This is the lowest layer, which is responsible for serializing and parallelizing the symbols of the data link layer, as well as generating and detecting electrical signals, as well as performing functions such as clock recovery, rate negotiation, and polarity reversal. The data unit of the physical layer is called a bit, which is the most basic transmission unit, which contains two states: 0 and 1.
Through such a hierarchy, the PCIe protocol can realize the efficient transmission and configuration of data, while also ensuring compatibility with the old PCI protocol, because the TLP format of the application layer is the same as the data format of the PCI protocol.
Finally, the PCIe protocol adopts the mechanism of BDF identifier and configuration space, which can realize the identification and configuration of devices. BDF is the abbreviation of bus, device, function, is a unique identifier for each PCIe device on the bus, which consists of three parts, namely bus number, device number and function number. The bus number occupies 8 digits to indicate the bus number of the device and supports up to 256 sub-buses. The device ID occupies 5 digits to indicate the position of the device on the bus, and supports up to 32 devices. The function number occupies 3 digits and represents different functions of the device, and supports up to 8 functions. For example, a NIC may have two functions, one is to send data and the other is to receive data, then it has two function numbers, 0 and 1, respectively. With BDF identifiers, we can uniquely determine the location and function of each PCIe device.
The configuration space is a memory area for each PCIe device that stores various information and parameters of the device, such as vendor ID, device ID, category code, status registers, interrupt vectors, etc. The size of the configuration space is 4 KB and is divided into two parts: the basic configuration space and the extended configuration space. The size of the basic configuration space is 256 bytes, which is the same as that of the PCI protocol, and is used to store basic information about the device. The size of the extended configuration space is 3840 bytes, which is used to store the extended information of the device, such as power management, thermal management, virtualization, etc. By configuring the space, we can read and modify the information and parameters of each PCIe device to realize the identification and configuration of the device.
Through this article, we learned what the PCIe protocol is, what features and advantages it has, and how it enables data transmission and configuration. We learned about the concepts of the PCIe protocol, such as hierarchy, bus architecture, BDF identifiers, configuration space, etc., as well as their role and significance. We also used some visual metaphors to help students remember and understand the principles of the PCIe protocol. It is hoped that students will be able to master the knowledge of PCIe protocol and use PCIe protocol technology to improve the performance and efficiency of computer systems.