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1.aiInspur has driven the demand for intelligent computing construction, and has taken the lead in the three major fields of computing power, storage power, and electric power
aiThe wave of large models kicked off the construction of computing infrastructure. The development of artificial intelligence has entered the era of large models from the era of deep learning, and the number of parameters of large-scale pre-trained models has increased exponentially, which requires the support of high-performance computing power. On the one hand, the innovation of algorithm structure has affected the design of AI chips in terms of computing power accuracy range and dedicated acceleration circuit, but the speed of increasing the computing power of a single chip still cannot catch up with the development rate of model parameters. On the other hand, due to the huge number of parameters and huge data samples, the size of the model has far exceeded the computing power of a single AI chip or even a single server, and models with more than 100 million yuan need to be deployed on multiple AI chips interconnected at high speed for distributed parallel training. At present, compared with the improvement of single-chip capabilities, the large-scale capability and efficiency of multi-chip clusters are the focus of industrial research.
AI computing clusters can provide large-scale computing power, continuously improve the utilization rate of computing resources, improve data storage and processing capabilities, and accelerate the training and inference efficiency of AI large models. At present, the more typical AI computing clusters, such as NVIDIA DGX SuperPod, Intelligent Cloud High-Performance Computing Cluster, and Tencent's next-generation high-performance computing cluster EHC HCC, continue to provide powerful computing resources for generative AI training scenarios, further reduce the threshold and cost of model training, and promote the implementation of generative AI models.
aiInspur promotes the construction of intelligent computing and drives the growth of demand for data center semiconductors.
The most significant feature of this period is the emergence of a huge quantitative trend of data and models, with hundreds of billions of models already emerging, which puts forward high requirements for the computing power and scalability of the intelligent computing base, and new technologies and methods that solve various challenges in bandwidth, latency, processing power, and power consumption will also drive market growth, such as GPGPU, AI ASIC, CXL, optical IO, CPO, or energy-efficient wide bandgap semiconductors. According to Yole**, the value of data center semiconductors will reach approximately $205 billion by 2029, growing at a CAGR of 128%, accounting for 65% of the entire server market, and also accounting for 26% of the entire semiconductor market.
Among the market segments, memory and processing are the largest in terms of market size, while optoelectronics and sensors have a high compound growth rate of 345%, which is driven by emerging optical chips for 400G and higher-speed optical transceivers. When the large model enters the scale of trillions of parameters, the demand for computing power, video memory and interconnection will be upgraded again, and the intelligent computing center will enter the era of super pooling, and the high-speed interconnected 100 cards will form a "super server", which is expected to become a new form of equipment, and it needs to build a unified protocol to realize the seamless connection of CPU, GPU, AI chips, video memory, storage and other pooled resources, so as to achieve extremely high throughput and extremely low latency system computing power.
The construction of computing power has driven the high growth of the telecommunications and infrastructure sectors, which in turn has driven the demand for advanced packaging.
From the perspective of the downstream application market segment of advanced packaging, according to Yole data, driven by the accelerated construction of the AI industry chain, the telecom and infrastructure sector has the fastest growth rate, with an expected annualized compound growth rate of 17%, and is expected to increase from 20% of the market share in 2022 to 27% in 2028. followed by the automotive and transportation sector, with an annualized compound growth rate of 10%, which is expected to account for 9% by 2028; The mobile and consumer sectors account for the majority of the advanced packaging industry and have a large market base, but are expected to achieve a compound annual growth rate of 7% between 2022 and 2028, driven by AI-enabled innovative consumer devices.
GraspaiInspur development opportunities, computing power, storage power, power three major areas of leading layout.
The wave of AI has promoted the rapid development of high-performance computing, and the company has created a system-level, one-stop packaging and testing solution that comprehensively covers the infrastructure of high-performance computing systems, namely computing modules, storage modules, power modules, and network modules. In the fields of computing power, storage capacity and power, the company has a mature technology platform and rich product experience, and the high-end manufacturing project of JCET wafer-level microsystem integration was capped in June 2023, which is a high-end production capacity layout built by JCET for global customers in the fast-growing market demand for high-performance computing (HPC) and artificial intelligence, and the project focuses on 2High-performance packaging technologies such as 5D 3D high-density wafer-level packaging can provide one-stop services from packaging co-design to chip production.
The third-generation semiconductor solutions in the power sector have matured and entered the stage of capacity expansion.
The third-generation semiconductors have advantages in high temperature and high voltage, high power, high current density and low on-resistance, and are widely used in the power field, but they are also accompanied by challenges such as parasitic inductance effects, package parasitic resistance, and electromagnetic interference. JCET and the world's leading customers jointly develop high-density integrated solutions that integrate a variety of packaging technologies, including Kelvin structure, flip technology, etc., to successfully reduce the interference of parasitic inductance. At the same time, the parasitic resistance of the package is reduced by using the clip and ribbon bonding process, thereby improving the power conversion efficiency. Secondly, the heat dissipation capacity of the package is directly related to the stability and efficiency of the power device, and the long-term solution greatly reduces the thermal resistance of the device and improves the heat conduction path through various technical means such as the top heat dissipation structure, which greatly improves the heat dissipation capacity of the package and helps the third-generation semiconductor device fully release the performance potential of the material. JCET's high-density finished product manufacturing solutions for the third generation of semiconductor power devices have matured and entered the stage of capacity expansion.
chipletOr become one of the ways to break the situation in the domestic advanced processxdfoitmThe technology platform is mature
chipletIt has a variety of advantages to break through the bottleneck of traditional chip design. Chiplet is one of the packaging solutions for high-performance chips, which can achieve larger chip size, break through the current manufacturing area limitations, and promote the continuous improvement of chip integration and computing power. Secondly, it breaks through the interconnection bandwidth and packaging bottlenecks of traditional packaging by introducing semiconductor manufacturing process technology. In addition, it breaks through the design cycle constraints under the scale of the core through the core level IP reuse and core prefabrication combination, and realizes the agile design of the chip.
Chip integration has a lot to offer in terms of improving computing power.
The earliest prototype of the integrated chip was a large-capacity FPGA chip V7200T jointly completed by TSMC and Xilinx, which connects four large-scale FPGA chips on a silicon substrate to form a system with more than 2000 programmable logic gates. And the background of Semiconductor Manufacturing has also completed chip-on-wafer-on-substrate (CODOS), which is currently this technology as 2The representative process of 5D integrated chips is widely used in high-performance processor chip products, taking NVIDIA's GP100 GPU chip as an example, its structure integrates GPU chips and multiple HBM chips in a package through CODOS to maximize the communication bandwidth between the processor and the memory. The Ascend 910 chip designed by Huawei HiSilicon is also based on this integrated technology to achieve a high-computing AI processor. In recent years, with the maturity of TSV, copper-copper hybrid bonding and other processes, 3D integrated chips have become a new development trend in the field of high-performance processors. AMD and Intel have designed high-performance supercomputing processor chips for supercomputing based on 3D integrated chip technology.
chipletTechnology is expected to become one of the "breakthrough" paths for China's advanced manufacturing process.
For example, in 2022, the Intelligent Computer Center of the Institute of Computing of the Chinese Academy of Sciences and the Zhijiang Laboratory jointly developed the "Zhijiang Big Chip No. 1", which integrates 16 chips, each of which contains 16 CPU cores. In 2022, the National Key Laboratory of Integrated Chips and Systems of Fudan University realized the integration of storage and computing based on the integrated fan-out packaging process2The 5D chip adopts a scalable architecture of inter-chip layer-by-layer flow, which realizes the linear growth of system computing power and storage scale according to the proportion of cores. In the context of the restricted development of high-performance chips, chiplet technology is expected to become one of the "breakthrough" paths for the advanced process of China's chip industry.
LaunchedxdfoiA full range of productshiplet, the process has been coveredc 4nmAdvanced manufacturing process and stable mass production.
JCET has launched a full range of XDFOI products, which is a new type of non-silicon through-hole wafer-level ultra-high-density packaging technology5D through-silicon via (TSV) packaging technology, with higher performance, higher reliability and lower cost, mainly focuses on FPGA, CPU, GPU, AI and 5G network chips and other application products with high requirements for integration and computing power, providing chiplet and heterogeneous packaging (HIP) system packaging solutions.
chipletIn terms of craftsmanship,At present, the XDFOI chiplet high-density multi-dimensional heterogeneous integration series process has entered the stable production stage as planned, and the 4nm node multi-chip system integrated packaging products of international customers have been shipped simultaneously, and the maximum package area is about 1500mm system-in-package. XDFOI chiplet is a high-density heterogeneous integration solution for chiplets, which uses the concept of co-design to realize the integration and testing of finished chips, covering 2D and 25D and 3D integrated technologies have been applied in high-performance computing, artificial intelligence, 5G, automotive electronics and other fields, providing customers with chip manufacturing solutions with thinner appearance, faster data transmission rate and lower power loss to meet the growing end market demand.
Publish the latestfo-aipEast Lake's wafer-level heterogeneous integration technology has a wide range of application fields.
Changdian Shaoxing project is one of the most important industrial projects of Shaoxing integrated circuit "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 The total investment of the project is 8 billion yuan, and the total planned area of the first phase is 228 acres. The second phase of the planning covers a total area of 150 acres, aiming at the application of integrated circuit wafer-level advanced manufacturing technology, and providing wafer-level advanced packaging products for chip design and manufacturing.
In June 2023, Changdian Integrated Circuit (Shaoxing)** released the newly developed FO-AIP East Lake wafer-level heterogeneous integration technology, which can be used in automotive intelligent driving, IoT millimeter wave sensing, Starlink communication and other fields.
The wave of AI large models has kicked off the construction of AI infrastructure, and the construction of intelligent computing has promoted the growth of demand for semiconductors in data centers, which in turn has driven the demand for advanced packaging. The company has taken the lead in the three major fields of computing power, storage power, and electric power, creating system-level, one-stop packaging and testing solutions, and the Changdian microelectronics project for high-performance computing (HPC) and artificial intelligence has been capped in June 2023. Chiplet breaks through the bottleneck of traditional chip design and has great promise in improving computing power, and is expected to become an advanced process in China.
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