With the popularization of intelligence, it may be necessary to use segment-code LCD display in many application scenarios, such as: household appliances, industrial equipment, instrumentation, building automation equipment, medical instruments, wearable devices, etc.
This is not only because the segment LCD has the advantages of beautiful display, cost advantage, low power consumption, etc., but also because many MCUs now integrate LCD driver modules, making development easier.
Today, we will tell you about the working principle of the built-in LCD control driver in the MCU in combination with the Renesas MCU.
Segment code LCD display LCD structure and display principle
Under the effect of the electrostatic field, the direction of the crystal arrangement will be deflected, thus changing its light transmittance, so that the displayed content can be seen. The LCD has a deflection threshold that displays content when the voltage across the LCD is higher than this threshold; Below this threshold, it is not displayed.
Generally, there are three main parameters for LCD in the segment code: operating voltage, DUTY (matching the COM number) and BIAS (bias voltage, matching the threshold), for example, 30V, 1 4Duty, 1 3Bias indicate that the operating voltage of the LCD is 30v, there are 4 coms, and the threshold is about 11v（3.0/3=1.0）。
When the voltage applied to both ends of a certain LCD is greater than 10v, otherwise, it is not displayed. However, the reaction of the LCD to the drive voltage is not very obvious, for example, add 1When the voltage is 0V, it may be faintly displayed, which is commonly referred to as "ghost". Therefore, it is necessary to ensure that when driving the LCD display, the voltage applied to both ends of the LCD is much larger than the threshold voltage, and when it is not displayed, it is much smaller than the threshold voltage.
It should be noted that the DC voltage can not be added to the two ends of the LCD, otherwise the electrochemical characteristics of the crystal molecular structure of the LCD crystal of the segment code LCD display will be endangered for a long time, resulting in the blurring of the actual effect of the display, the adverse effects of the reduction of the service life, and its devastating can not be repaired, which requires that the average voltage of the driving voltage added to both ends of the LCD is 0. Therefore, LCD uses the split scanning method, and only one COM scan is valid at any one time, and the rest of the COMs are invalid.
A good segment-coded LCD LCD controller driver should meet:
It can provide different numbers of COM, DUTY (matching COM number) and BIAS (bias voltage, matching threshold) to meet the driving requirements of different specifications of LCD screens.
It can provide a variety of voltage divider methods, provide internal voltage division, and reduce the voltage division of peripheral circuits.
It can provide an internal boost boost to meet some battery power, and the brightness can be maintained when the battery voltage drops.
It can provide internal reference voltage regulation to avoid "ghosting" of the display due to inaccurate voltage division
Multiple different reference voltage options are available, and the contrast ratio can be adjusted.
It can provide a variety of different segmentation scanning methods and drive waveforms to meet flexible choices.
It can choose from different clock sources and different split scanning frame rates to meet the low power requirements of different applications.
The LCD controller driver built into the Renesas MCU not only meets the above specifications, but also provides other advantageous features:
Different clock source options are available, with the option of an external sub-clock32768kHz, with a choice of internal MCU low-speed or high-speed clock.
A display data register is provided, and the display data register can be automatically output for segment signal SEG and common signal COM by automatically reading the display data register.
Provides a time interval blinking function for convenience and ease of use.
The Renesas MCU has a built-in LCD controller driver
LCD controller drive block diagram
Figure 1 shows the integration into Renesas' own 16BITS RL78 series core MCUsLCD controller driversFigure 2 integrates the LCD controller in the Renesas 32BITS RA4M1 series ARM core MCU driver, and the main differences between the two are:LCD controller driversThe RA4M1 series also supports the selection of an internal high-speed clock.
Figure 1 R7F0C001 R7F0C002 L12 L13 L1A L1C LCD controller driver.
Figure 2 RA4M1 LCD controller driver.
Peripheral Permissible Register 0 (Per0): Sets when using the sub-system clock (FSUB) for the LCD controller driver.
LCD Mode Register 0 (LCDM0): The LCD drive voltage generation circuit, the display waveform (A B), and the display of the time slice duty.
LCD Mode Register 1 (LCDM1): This register allows or disables display operation, allows or disables the operation of boost circuits and capacitor splitting circuits, and sets display data areas and low voltage modes.
Running Speed Mode Control Register (OSMC): Reduces power consumption by stopping unwanted clock functions.
LCD Clock Control Register 0 (LCDC0): Sets the registers of the LCD source clock and the LCD clock, and determines the frame rate by the LCD clock and time slice.
Memory Liquid Crystal Control Register (MLCD): Controls the memory liquid crystal waveform.
LCD Boost Level Control Register (VLCD): You can choose from 16 reference voltages (adjust contrast) generated while the boost circuit is running.
LCD Input Switching Control Register (ISCLCD): Prevents the inflow of feed-through current during the operation of the CAPL P126, CAPH P127, and VL3 P125 pins as LCD functions.
LCD Controller The driving waveform of the driver
The driving waveform includes the COM port waveform, the SEG port waveform, and the voltage difference waveform between COM and SEG, when the potential difference between COM and SEG corresponding to each pixel is higher than a certain voltage (LCD driving voltage VLCD, that is, the threshold voltage), each pixel of the LCD display will be lit. If the potential difference is lower than the VLCD, the lights are turned off for each element.
com port waveform.
According to the set time slice, the sequence shown in the table is the selected time series of the common signal, and the operation is repeated as a cycle. In the case of static mode, COM0 COM3 outputs the same signal.
SEG port waveform.
The SEG signal corresponds to the LCD display data register, and in the case of 8 time slices, the BIT0 and BIT7 of each display data register correspond to COM0 COM7. Synchronizes with each timing of the common signal output and reads data from the data memory. If the content of each bit is "1", it is converted to the selected voltage and output to the segment pin (SEG4 SEG38). If the content of each bit is "0", it is converted to a non-selected voltage and output to the segment pin (SEG4 SEG38).
In the case of a non-8-slice time slice method, BIT0 BIT3 of each data register is displayed in the A graphics area, and BIT4 and BIT7 of each data register are displayed in the B graphics area, corresponding to COM0 COM3. Synchronizes with each timing of the common signal output and reads data from the data memory. If the content of each bit is "1", it is converted to the selected voltage and output to the segment pin (seg0 seg38). If the content of each bit is "0", it is converted to a non-selected voltage and output to the segment pin (seg0 seg38).
Therefore, it is necessary to check how the front electrodes (corresponding to the SEG signal) and the back electrodes (corresponding to the COM signal) of the LCD display used by the LCD display data register are combined to form a display graph, and then write the bit data corresponding to the display graphic to the display data register.
Output waveforms of COM signals and SEG signals.
The voltages of the common signal COM and segment signal SEG outputs are shown in Table (a)-(D). The lighting voltage of the VLCD is only selected when both the common signal COM and the segment signal SEG are selected voltages, and the lights-out voltage (not selected) in other combinations.
In static display mode, the output waveform of the common signal COM belongs to the LCD clock for 1 cycle T (selected or non-selective), the front T 2 outputs VL4 partial voltage level, and the rear T 2 outputs VSS level; The output waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the front T 2 outputs the VSS voltage divider level, the rear T 2 outputs the VL4 level, and the rear T 2 outputs the VL4 voltage level when it belongs to the non-selected 1 cycle T, the front T 2 outputs the VL4 partial voltage level, and the rear T 2 outputs the VSS level.
1 2 when bias, the output waveform of the common signal COM, when the LCD clock belongs to the selection of 1 cycle T, the front T 2 output VL4 partial voltage level, the rear T 2 output VSS level, belongs to the non-selected 1 cycle T, the output VL2 level; The output waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the front T 2 outputs the VSS voltage divider level, the rear T 2 outputs the VL4 level, and the rear T 2 outputs the VL4 voltage level when it belongs to the non-selected 1 cycle T, the front T 2 outputs the VL4 partial voltage level, and the rear T 2 outputs the VSS level.
1 3 when biased, the output A waveform of the common signal COM, 1 cycle T when the LCD clock belongs to the selection, the front T 2 output VL4 partial voltage level, the rear T 2 output VSS level, belongs to the 1 cycle T when it is not selected, the front T 2 output VL1 partial voltage level, and the rear T 2 output VL2 level; The output A waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the front T 2 outputs the VSS voltage divider level, the rear T 2 outputs the VL4 level, belongs to the non-selected 1 cycle T, the front T 2 outputs the VL2 partial voltage level, and the rear T 2 outputs the VL1 level.
1 3 When biased, the output B waveform of the common signal COM belongs to 1 cycle T when the LCD clock belongs to selection, the first T 2 (in the first half of the frame TF 2) outputs VL4 partial voltage level, the rear T 2 (in the second half of the frame TF 2) outputs the VSS level, belongs to the non-selected 1 cycle T, the first T 2 (in the first half of the frame TF 2) outputs VL1 partial voltage level, and the rear T 2 (in the second half of the frame TF 2) outputs VL2 level; The output B waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the first T 2 (in the first half of the frame TF 2) outputs the VSS divider level, the last T 2 (in the second half of the frame TF 2) outputs the VL4 level, belongs to the non-selected 1 cycle T, the first T 2 (in the first half of the frame TF 2) outputs the VL2 partial voltage level, and the last T 2 (in the second half of the frame TF 2) outputs the VL1 level.
1 4 when the bias, the output A waveform of the common signal COM, in the LCD clock belongs to the selection of 1 cycle T, the front T 2 output VL4 partial voltage level, the rear T 2 output VSS level, belongs to the non-selected time of 1 cycle T, the front T 2 output VL1 partial voltage level, the rear T 2 output VL2 level; The output A waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the front T 2 outputs the VSS voltage divider level, the rear T 2 outputs the VL4 level, belongs to the non-selected 1 cycle T, the front T 2 outputs the VL2 partial voltage level, and the rear T 2 outputs the VL2 level.
1 4 When biased, the output B waveform of the common signal COM belongs to one cycle T when the LCD clock belongs to selection, the first T 2 (in the first half frame TF 2) outputs VL4 partial voltage level, the rear T 2 (in the second half frame TF 2) outputs VSS level, belongs to the non-selected 1 cycle T, the first T 2 (in the first half frame TF 2) outputs VL1 partial voltage level, and the rear T 2 (in the second half frame TF 2) outputs VL3 level; The output B waveform of the segment signal SEG is 1 cycle T when the LCD clock is selected, the first T 2 (in the first half of the frame TF 2) outputs the VSS partial level, the last T 2 (in the second half of the frame TF 2) outputs the VL4 level, belongs to the non-selected 1 cycle T, the first T 2 (in the first half of the frame TF 2) outputs the VL2 partial voltage level, and the last T 2 (in the second half of the frame TF 2) outputs the VL2 level.
Examples of output waveforms for COM signals and SEG signals.
In this example, take the 7th place.
Explain. The selected and non-selective voltages shown in the table need to be output to the SEG12 and SEG13 pins according to the display pattern and the timing of each common signal via COM0 COM3.
Therefore, it is sufficient to prepare "1101" for the display data register (address F040CH) corresponding to SEG12. An example of an LCD-driven waveform between SEG12 and each common signal is shown in the figure below. When selecting COM0 as the selected voltage, SEG12 is the selected voltage, and the generation of the AC rectangular wave of the LCD lighting level + VLCD VLCD is known.
Example of an LCD-driven A waveform with 4 time slices between SEG12 and each common signal (1-3 bias method).
Example of an LCD-driven B waveform with 4 time slices between SEG12 and each common signal (1-3 bias method).
LCD Controller The driving voltage of the driver
LCD drive voltages VL1, VL2, VL3, VL4 are provided, which are divided into internal boost, capacitor splitting, and external resistor splitting.
Internal boost. For example, R7F0C001G L and R7F0C002G L have built-in internal boost circuits for LCD drive power supplies. Capacitors (047 F 30%), generating the LCD drive voltage. The internal boost method can only be used using the 1 3 bias method or the 1 4 bias method.
The LCD drive voltage of the internal boost method is not the same as the device itself, so it is independent of the change in VDD, and a fixed voltage can be provided.
The contrast can be adjusted by setting the LCD boost control register (VLCD).
Capacitance splitting. For example, R7F0C001G L and R7F0C002G L have built-in capacitance splitting circuits for driving power supplies. Capacitors (047 F 30%), generating the LCD drive voltage. The capacitor splitting method can only use the 1 3 bias method. Unlike the external resistor splitting method, the capacitor splitting method does not flow current, so the current consumption can be reduced.
External resistance splitting.
LCD controller for driver clock control
LCD Controller Data-driven display of the drive.
You can choose from 16 types of reference voltages (adjust contrast) generated during the operation of the boost circuit.
LCD Controller Data-driven display of the drive.
When used for static, 2-, 3-, or 4-time slices, such as R7F0C001G L and R7F0C002G L, you can select the LCD display data register from the following three types by setting the BLON bit and the LCD sel bit
A Graphics area (LCD displays the lower 4 bits of the data register) for data display.
B. Display of data in the graphic area (the LCD displays the upper 4 bits of the data register).
Alternate display of data from the A and B graphics areas (flashing display corresponding to the fixed period interrupt timing of the real-time counter (RTC)).
Note that when using 8 time slices, the LCD display data registers (A graph, B graph, or flashing display) cannot be selected.
Flashing display (alternate display of data in the A and B graphics areas) R7F0C001G L, R7F0C002G L Example.
When the BLON bit is "1", the data in the A and B graphics areas are displayed alternately in accordance with the fixed period interrupt (INTRTC) timing of the Real-Time Counter (RTC). When the LCD flashes, the inverting value (ex.) must be set to the bit of the B graphic area corresponding to the bit in the A graphic areaSet the bit0 of F0400H to "1", and set the bit4 of F0400H to "0" when flashing); When the LCD is not flashing, the same value (ex.) must be setSet bits 2 of F0402H to "1", and set bits of F0402H to "1" when the lights are on.
The switching timing displayed is shown below.
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