TSMC held the opening ceremony of Kumamoto's first wafer factory on February 24, compared with the postponement of the American factory, the Japanese factory has been generally smooth since the announcement of the establishment of the factory.
A few days ago, Semiconductor Manufacturing Company announced the construction of a second wafer factory, and on the other hand, the progress of the new factory was back on track after the U.S. factory signed an agreement with the labor union before.
The German factory is now fully assisting TSMC to build a factory, hoping to give full play to the industrial magnetic attraction effect, build a strong semiconductor industry chain and activate the development of local industries.
It is worth noting that TSMC's overseas expansion continues to be carried out, and Intel, which has returned to the battlefield of wafer foundry, has already invested heavily in global production deployment.
At the same time, Intel also has strong support from the United States, obtained multi-party financial subsidy support, coupled with the development of advanced process technology for many years, and maintains a leading position in innovative technology and material application.
The construction of the U.S. factory is more difficult than expected
Since the announcement of the new factory in the United States in 2020, the new factory in Kumamoto, Japan, was also revealed in 2021, and the blueprint of the German factory will be released as expected in 2023, and mass production is expected to be produced by the end of 2027.
The United States, Japan and Germany took shortcuts to strengthen the strength of the semiconductor industry chain, and TSMC became the target for various countries.
However, in recent years, in the face of the expected recovery of the economy, coupled with the pressure of geopolitical risks, TSMC's expansion plan has been completely disrupted by external intervention, and uncertainties have increased significantly.
Especially in the United States, the road to factory construction has stumbled all the way, affected by complex issues such as market demand, local regulations, labor regulations, work culture and soaring costs, the original first phase of the project began to produce 5nm process technology in 2024, and then revised to 4nm, and postponed to the first half of 2025 mass production.
The second phase of the project, which is being built at the same time, is expected to start producing 3nm process technology in 2026, but the statement of the former TSMC has become vague, and the mass production schedule will be postponed to 2027, and what kind of process technology will be adopted in the end, it will also be changed depending on customer needs, and it is being discussed with relevant units in the United States, that is, it will not necessarily be a 3nm process, and there is still room for change.
The total investment in the second phase of the U.S. plant project soared to $40 billion, making it the largest FDI project in Arizona history and one of the largest in U.S. history.
Apple prompted the rapid construction of factories in Japan
Compared with the difficulty of building a factory in the United States, TSMC has built a factory in Japan relatively smoothly.
The first Kumamoto factory started construction in April 2022, 24 hours to complete the work, less than 2 years to complete and real mass production, although not advanced process, but in the civil steel structure, clean room construction and various factory progress is quite fast, Japan's best support, similar labor culture is the key.
It is understood that it is Japan's top five construction companies that help TSMC build factories, and TSMC has also brought its own closely coordinated work classes and factory equipment, etc., so in place, the right people are in place, the progress of the Kumamoto factory is in line with expectations, and profits are expected to be realized in advance.
DSMC announced that it has partnered with Sony Semiconductor Solutions Corporation (SSS), Denso and Toyota to invest in a second fab, which is scheduled to start operations by the end of 2027, with a total monthly production capacity of more than 100,000 12-inch wafers, providing 40nm, 22 28nm, 12 16nm and 6 for automotive, industrial, consumer and high-efficiency computing (HPC) related applications 7nm process technology, which is also the first advanced process node in Japan that can truly have mass production below 7nm EUV.
In addition, it is also rumored that the two sides have also begun to discuss the construction plan of the third phase of the wafer factory.
Why TSMC quickly decided to set up a factory in Japan, Wei Zhejia bluntly said that Japan is indeed not a cheap place, and the main reason for deciding to set up a factory is the requirements of the largest customer, hoping to fully assist its largest business.
TSMC's core consideration has always been to give priority to customer needs, customers' products cannot be sold, and TSMC's 3nm and 5nm have no orders, so we must fully support them.
It is understood that TSMC's largest customer is Apple, accounting for about 25% of revenue, and Sony is an important supplier of iPhone image sensors.
Judging from the purpose of TSMC's construction of factories in Japan and its joint venture partners, it is obvious that it will stick to Apple's orders, as well as Japan's best efforts to expand automotive and industrial applications and seize the new battlefield of HPC and AI.
The Kumamoto Plant is expected to create a total of more than 3,400 jobs directly, with an estimated total of nearly 9,000 jobs combined with indirect manpower requirements.
In terms of salary level, TSMC's basic monthly salary is 280,000 yen for university graduates, 320,000 yen for master's graduates, and 360,000 yen for doctoral graduates, which is more than 50,000 yen higher than the national average in Japan, and it also accelerates the attraction of talents and the development of the local economy.
Full support from Japanese equipment and material manufacturers
It is worth noting that TSMC has another major consideration for going to Japan, that is, semiconductor wafer manufacturing requires a total of more than 1,000 processes, and Japan has a market share of about 3% of the global equipment market with the United States, although it does not have ASML's exclusive EUV technology equipment, but it has a key position in key components.
In addition, Japan has nearly 50% of the world's territory in key materials such as photoresists, slurries, etching gases and silicon wafers.
This is why TSMC established a technical center in Yokohama in January 2020 and a 3DIC R&D center in Japan in Tsukuba City, Ibaraki Prefecture in March 2021.
Among them, the 3DIC R&D center can cooperate with Japanese partners, research institutes and universities with advantages in semiconductor materials and equipment to assist in the research and development of the most advanced 3D integrated circuit packaging materials.
It is worth mentioning that for Europe, the United States, Japan and Southeast Asia, many countries are making every effort to rebuild the local semiconductor manufacturing chain, who will succeed?
Zhang Zhongmou also said that many countries want to build a manufacturing chain, among which Japan is an ideal place, especially Kyushu has advantages in water, electricity and land, and the work culture is also quite good.
At the same time, it also warns that with the evolution of Taiwan's economic development and other situations, in 20-30 years, the semiconductor manufacturing environment may not be in a favorable position as it is now.
The value of semiconductor production will reach $1 trillion in 2030
According to Intel's CEO Pat Gelsinger, AI is helping to drive the "silicon economy" of continued growth driven by chips and software. Chips have created a $574 billion industry and driven the global tech economy to nearly $8 trillion.
From 1995 to 2015, semiconductor innovation reached about $3 trillion in global GDP and $11 trillion in indirect output, and the growth of the semiconductor industry continues to accelerate.
Global semiconductor shipments in 2021 were 115 trillion, with a projected growth rate of 10 by 20244%, which is expected to be a $1 trillion industry by 2030.
The semiconductor business opportunities and the overall scale of the industry continue to expand, which is the key for Intel to continue to promote advanced manufacturing processes and global production expansion to meet the huge demand.
Intel's global expansion is not soft
Intel currently has eight manufacturing sites around the world, including two in Arizona, two in Ohio, one in Israel, and two new fabs in Germany, bringing the number of fabs to 15.
In terms of new fabs: there are Fab 12, Fab 22, Fab 32 and Fab 42 fabs in Arizona, USA; Oregon has TD Fabs D1; Ireland has Fab 24 and Fab 34;Israel for fab 28;Planned are Ohio and German plants.
Test and assembly plants include Costa Rica, China, Malaysia and Vietnam; The advanced packaging facility is located in New Mexico, with a planned facility in Malaysia.
Intel says putting billions of tiny transistors into smaller and smaller computing chips is one of the most complex manufacturing processes for humanity.
A fully equipped new FAB cost at least $10 billion and will take 6,000 workers about three years to complete. Intel's manufacturing operations are global in size and require a global ** chain that spans different continents.
Intel further noted that it announced more than $43.5 billion in investments in Arizona, New Mexico, and Ohio in 2021 to strengthen U.S. chip manufacturing and R&D leadership.
These investments have grown significantly to date, not even counting investments in R&D and accelerating technological development.
Intel's announced investments include expanding its operations in Arizona, where it has invested for more than 40 years, from two to four plants, each estimated to cost between $15 billion and $20 billion.
In New Mexico, at least $3.5 billion will be invested in packaged equipment upgrades. The greenfield investment in two plants in Ohio will be the largest investment in the state's history.
In Oregon, Intel is in the planning phase and is ready to invest billions of dollars in equipment expansion and modernization. This will allow Intel to regain its leadership in process technology and continue to push Moore's Law forward.
Intel has also announced plans to invest more than 33 billion euros in an initial investment to build a factory in Germany, establish an R&D and design center in France, and expand R&D capabilities, manufacturing, foundry services and back-end production in Ireland, Italy, Poland and Spain.
Through this series of plans, Intel will bring its advanced technology to Europe, assist the EU in creating the next European chip ecosystem, and meet the global demand for a more balanced and resilient ** chain.
As Intel IDM 2As part of Strategy 0, Intel's program will help increase production capacity to meet the growing demand for advanced semiconductors, power Intel's next generation of innovative products, and meet the needs of foundry customers.
The semiconductor assembly and test plant near Wroclaw, Poland, is expected to invest USD 4.6 billion.
Poland was chosen as the location for the new plant due to its infrastructure, talent, and excellent business environment. The construction will also enable close collaboration with Intel's planned fabs in Germany and existing fabs in Ireland to help improve the cost efficiency of semiconductors in Europe and support the EU's goal of achieving 20% of global semiconductor capacity by 2030.
Advanced manufacturing process and advanced packaging advancement
In terms of advanced process technology advancement, Intel has established a 4-year 5-node plan (5N4Y) to proceed as scheduled, and is expected to restore its leadership in transistor performance and power consumption by 2025.
At the IFS conference, the new plan for advanced manufacturing processes from 2025 to 2027 after Intel 18A was released, including Intel 14A and 14A-E, which will lead the introduction of High-NA EUV, as well as the upgraded Intel 18A-P, as well as Intel 3-E and Intel 3-PT. It is also the latest to include a collaboration with UMC on the 12nm process.
In terms of partners, it has cooperated with 34 companies in the IP, EDA and other industries, and has formed alliances with Cadence and ANSYS in the EDA of Intel 18A and 14A, and IP companies include ARM, Taiwanese manufacturers M31, Andes Technology, etc.
In terms of advanced packaging, Intel technology continues to lead the industry to continue Moore's Law.
In addition to promoting the upgrade of the overall system computing performance, it also controls the power consumption within a certain range as much as possible to avoid excessive impact of heat dissipation problems in the system design, which will bring additional burden and impact to the system design.
For this reason, the industry has begun to promote HBM to stack multiple bare cores with TSVs (Through-Silicon VIA), and then use silicon substrates as the basis to connect the stacked HBMs with a variety of computing chips of different architectures, such as CPUs, GPUs, and FPGAs.
Intel EMIB has been shipping products since 2017, with the first 25D embedded bridging solutions continue to lead the industry.
Sapphire Rapids is the first mass-produced XEON data center product with MIB.
It is also the industry's first device with a 4-cube chip, providing performance equivalent to a single-chip design. After Sapphire Rapids, the next generation of EMI will be reduced from 55 microns to 45 microns.
Drawing on the advantages of wafer-level packaging capabilities since 2020, Foveros has provided the first 3D stacking solution, Meteor Lake is the second generation of Foveros to be implemented in client products, with 36 micron bump pitch, chip blocks across multiple process nodes, and thermal design power consumption from 5 to 125 watts.
Co-EMIB began to combine EMIB and FoverOS technologies in 2022, and Intel launched the GPU MAC series, codenamed Ponte Vecchio.
Co-EMIB scales across all three dimensions of Ponte Vecchio, adding 11 bridges, 47 active chip blocks, 5 different nodes, and 100 billion transistors, making it the most complex packaging technology Intel has ever made.