Take the N-channel planar MOS as an example, as shown in the following figure.
The establishment of turn-on is the creation of an n-drift region between the two n+ regions of the source drain. As shown in the figure, the PN junction J2 is shorted by the source metal, and the built-in electric field of the PN junction J1 is directed from right to left horizontally, and when a positive voltage is applied to the drain, the PN junction J1 is reversed, and no current flows through the drain source when no bias voltage is applied to the gate. When the positive voltage applied to the gate exceeds the gate opening voltage vth of the MOS, an electron-filled inverse layer (inversion channel in the figure) is formed below the gate stage, forming a MOS conduction channel.
When the voltage of the drain is very small (VD《(VG-VTH)), the thickness of the whole channel is basically the same, and the channel impedance is basically unchanged. When the channel current rises, a right-to-left voltage difference is formed in the channel due to the channel resistance, which will cancel out part of the gate bias voltage, making the channel narrow at the drain end, as shown in the figure below.
As the current continues to rise, the drain voltage rises to an equal to the bias voltage (VD=(VG-VTH)). When the channel is close to the drain terminal, there is no voltage in the inverted layer, forming a channel pre-clamping. The drain current is saturated, and the magnitude of the drain current is determined by the gate bias, as shown in the figure below.
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