Among the many resonant converters, LLC resonant converters have the most common topologies for high power density applications. Earlier we covered design considerations for a half-bridge LLC resonant converter with the NCP4390, which includes an explanation of how the LLC resonant converter works, the design of the transformer and resonant networks, and the selection of components. Today we will go through the first 9 steps of the design program with design examples to help you complete the design of your LLC resonant converter.
Design the program
This article describes a design procedure that uses the circuit diagram in Figure 12 as a reference, where the resonant inductance is implemented using the leakage inductance. The design specifications are as follows:
Nominal input voltage: 396 VDC (PFC level output).
Output: 24 V 12 A (288 W).
Retention time requirement: 20 ms
DC link capacitance for PFC output: 330 F
[Step-1] Define the system specifications
As a first step, define the following specifications.
Estimated Efficiency (EFF): Estimates the power conversion efficiency to calculate the maximum input power for a given maximum output power. Based on the estimated efficiency, the maximum input power is:
Input Voltage Range: The maximum input voltage will be the nominal PFC output voltage.
Although the PFC pre-regulator regulates the input voltage, it also drops during the hold time. The minimum input voltage for the required hold time is:
where voPFC is the nominal PFC output voltage, THLD is the hold-up time, and CBLK is the DC link bulk capacitance.
Design examples
Assuming an efficiency of 96%,
For a hold time of 20 ms, the minimum input voltage can be obtained as .
For greater margin, the minimum input voltage is set at 300V.
[Step 2] Determine the voltage gain range of the resonant network
Once the minimum and maximum input voltages of the LLC resonant converter have been determined, we can determine the minimum and maximum gain of the LLC converter.
The nominal input voltage requires a minimum gain. To minimize switching frequency variations, LLC resonant converters are typically operated near the resonant frequency. The voltage gain at the resonant frequency is:
During the hold time, the PFC output voltage (the input voltage of the LLC resonant converter) drops, so a higher gain is required to regulate the output voltage. The maximum voltage gain is:
We can use a smaller m-value to get a higher peak gain; However, if the m-value is too small, it will lead to poor coupling and reduced efficiency of the transformer. It is common to set the m value too small at around 3 7.
Design examples
The ratio (m) between LP and LR is chosen 569。The minimum gain is obtained by:
The minimum gain at the maximum input voltage is selected as 113。Then, we can get the maximum gain of the minimum input voltage of .
Figure 13: Maximum Gain Minimum gain.
[Step 3] Determine the transformer turns ratio (n=np ns).
Using the minimum gain (mmin) obtained in step 2, we can calculate the number of transformer turns, as shown below
Design examples
Since SR is used for the output rectifier, it is useful for those with low RDSOn the SR MOSFET, VF is assumed to be 0V. From this, the ratio of transformer turns can be obtained.
[Step 4] Calculate the equivalent load resistance
Using the transformer turns ratio obtained from equation (16), we can calculate the equivalent load resistance.
Design examples
[Step 5] Design the resonant network
After selecting the m-value in step 2, read the appropriate q-value from the peak gain curve in Figure 10 to obtain the desired maximum gain. Since the peak gain curve is generated using a fundamental approximation, the actual gain at resonance is about 10 15% higher than the ** value using the fundamental approximation.
Once the q value is determined, we can obtain the following resonant components:
Design examples
As calculated in step 2, the mmax is 149。In step 2, select 569。From the peak gain curve in Figure 14, the maximum q value is 037。
Figure 14: Resonant network design using peak gain (maximum achievable gain).
By choosing the resonant frequency as 95kHz, the resonant components are determined as follows:
When the transformer is built, the actual parameters are adjusted as follows to accommodate the standard component values at CR = 48 nF, LR = 58 h, LP = 330 h, and FO = 95 kHz.
The gain curve of the final resonant network design using the fundamental approximation is as follows.
Figure 15: Gain curve for a design example.
Since the fundamental approximation yields a peak gain that is 10 15% lower than the actual peak gain when operating below resonance, we performed a simplis ** to see the actual gain. **The results show that at 75kHz, the maximum gain required is obtained with a 300V input. **The results also show a switching frequency of 105kHz at nominal input voltage and full load.
Figure 16: VIN = 300 V, FS = 69** at 55 kHz, PO = 288 W.
Figure 17: VIN = 396 V, FS = 105 kHz, PO = 288 W.
[Step 6] Design the transformer
Figure 18 shows the excitation current of a transformer in an LLC resonant converter. The minimum number of turns required for the primary side winding to limit the maximum magnetic flux density bmax is obtained by:
where AE is the cross-sectional area of the transformer core in m2 and Bmax is the maximum flux density swing in Tesla, as shown in Figure 18. If no reference data is available, bmax = 02~0.3 t to reduce core losses. Note that the equation ** shows the virtual gain mv due to the secondary side leakage inductance (see Figure 7).
Figure 18: Magnetic flux density swing.
Choose the appropriate number of turns for the secondary side so that the number of turns on the primary side is higher than npmin.
The wire gauges for the primary and secondary side windings should be determined based on the RMS current at the nominal input voltage, given by the equation below.
Design examples
SRV5018 core (AE = 189.) is used for the transformer2 mm2)。bmax is selected as 01t to reduce the core loss of the transformer. The minimum number of primary turns of a transformer is.
ns, 3;NP option 28.
At the nominal input voltage, the rms current of the transformer winding can be obtained as.
[Step 7] Select the resonant capacitor
Figure 19 shows the waveforms of primary-side currents (resonant capacitive currents) under different operating conditions. When selecting a resonant capacitor, the rated current should be taken into account, as a large amount of current will flow through the capacitor. The RMS current through the resonant capacitor at the nominal input voltage has been obtained in Equation (23).
The maximum resonant capacitance voltage under nominal input voltage and nominal load conditions is given by:
The rated voltage of the resonant capacitor should be determined based on the maximum voltage at each corner condition.
The maximum resonant capacitance voltage under nominal input voltage and output overcurrent conditions is given by:
The minimum input voltage and the maximum resonant capacitance voltage under nominal load are given by:
Note that in the case of a full-bridge LLC, the VIN 2 entry in equation (25) 27) should be removed.
Figure 19: Primary-side current waveforms of an LLC resonant converter in different operating modes.
Design examples
In step 6, the rms current of the resonant capacitor is calculated as follows:
The nominal input voltage and the maximum resonant capacitance voltage under nominal load are obtained by:
By setting the OCP level to 13A, the maximum resonant capacitance voltage under the nominal input voltage and output overcurrent conditions can be obtained.
By setting the minimum frequency to 65 kHz, the minimum input voltage and the maximum resonant capacitance voltage under nominal load can be obtained.
[Step 8] Rectifier network design
When a center-tapped winding is used on the secondary side of the transformer, the diode voltage stress is twice as high as the output voltage.
The rms value of the current flowing through each rectifier diode is given by:
At the same time, the ripple current flowing through the output capacitor is given by:
The voltage ripple on the output capacitor is.
Design examples
The voltage stress and current stress of the rectifier diode are:
Considering the voltage overshoot caused by stray inductance, 75 V 45 m Powertrench MOSFETs as synchronous rectifiers. The conduction loss on each MOSFET is 047w。
The rms current of the output capacitor is:
The output capacitors are connected in parallel using four 1200 F capacitors. The rated current and ESR of each capacitor are 2., respectively77 arms and 15 m.
The output capacitance ripple is calculated as follows.
[Step 9] Current sense circuit configuration
Figure 20: Typical current sensing configuration.
The NCP4390 will sense the instantaneous switching current and the integration of the switching current, as shown in Figure 20. Since the NCP4390 is located on the secondary side, a current transformer is used to sense the currents on the primary side. When Prout1 is low, an internal reset switch clamps the ICS pin voltage to 0 V. Conversely, when Prout1 is high, the ICS pin is not clamped and the integral capacitance (CICS) is charged and discharged by the current flowing through the RICS resistor.
The application circuit of the NCP4390 uses an RC filter for quasi-integration. For accurate integration, the ratio of turns of the current sense resistor and current transformer should be designed in such a way that the amplitude of the VSsense is higher than that of the VICS most of the time. Figure 23 shows how the error of the quasi-integrating circuit at the falling edge of Prout1 (VCM) varies with the ratio between the VICS peak voltage and VSENSE. The smaller the ratio, the more accurate the integration.
When the ratio between the peak voltage of the VICS and the VCM is less than 05, a quasi-integral with an acceptable error (about 10%) is obtained. Due to normal operation, the peak voltage of the vics is less than 12V, so we should choose RCS1 and RCS2 so that VCM is higher than 24v。
Figure 21: ICS pin waveform.
Figure 22: VICSiThingPK and VicsDefinition of actualpk.
Figure 23: ICS pin voltage attenuation vs. VICSidealpk/vcm
To get the peak voltage of the VICS, let's take a look at the ideal input power of the LLC converter. For a half-bridge LLC topology, with the PROUT1 on-time defined as T=0, the input power can be expressed by:
Note that in the case of a full-bridge LLC, the right side of the equal sign should be multiplied by 2.
Assuming that the integration is ideal, the peak voltage of ICS can be expressed by:
Combining (33) and (34), the ICS peak voltage can be estimated by:
Considering the ability of the ICS pin to discharge the switch internally, the typical value for the CICS is 1 nF. For accurate integration, we recommend using a capacitance with a 1% tolerance.
When the ratio between the peak voltage of the VICS and the VCM is not small enough, apply the attenuation factor from Figure 23 to equation (35).
The peak value of the current sense voltage (VICS) integration is proportional to the average input current of the LLC resonant converter during the switching cycle, as shown in Figure 24. Therefore, based on the percentage of the rated power corresponding to the input current limit threshold, the SR enabled Disabled load condition is determined as the percentage of the full load condition. Typically, a rated load condition of 120% is used for the overcurrent trip point, with SR at 15% and 7., respectivelyEnabled and disabled at 5% rated load. If the overcurrent trip point has a rated load condition of 140%, the SR will be at 17 of the rated load5% and 8Enabled and disabled 75% of the time.
In order to achieve a higher overcurrent limit without increasing the SR enable disable point, an additional slope can be applied on the VICS via the resistor RSLP between the ICS and the 5VB pin. This technique is often used in the case of longer hold times. For a given RSLP, the additional slope applied for the ICS pin voltage is given by:
Figure 24: Load conditions and ICS pin voltage.
Figure 25: Current sensing configuration with slope compensation.
Figure 26: Load conditions and ICS pin voltages when slope compensation is increased.
The rated input voltage and the peak current-to-primary side at full load are estimated by the following formula:
The ratio between RCS1 and RCS2 is determined based on the primary-side overcurrent protection (OCP) trip point, which should be less than the IPR PK.
Design examples
For a current transformer with a turns ratio of 44 (NCT), the minimum recommended value for the sum between RCS1 and RCS2 is given by:
Since the power consumption is not too high, RCS1 + RCS2 can be set higher to get the ideal points on the VICS. From this, we choose the sum of rcs1 and rcs2 as 230.
The rated input voltage and the peak currents on the primary side at full load are given by:
By setting the primary-side OCP level to 5A:
RCS1 and RCS2 choose 30 and 200, respectively.
This design does not impose additional slope on the ICS pins.
Select CICS as 1 nF capacitance. Hypothesis 1The attenuation factor for the VICS at 2 V is 10 (x=1. in Figure 23.)2/10.23 readings), then 13 A overload protection (IOolp) is .
Select RICS as 30 k.
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