Many of today's precision analog-to-digital converters (ADCs) have a serial peripheral interface (SPI) or some sort of serial interface to communicate with controllers including microcontroller units (MCUs), DSPs, and FPGAs. The controller writes or reads the ADC's internal registers and reads the conversion code. SPI is becoming increasingly popular due to its simple printed circuit board (PCB) routing and faster clock rates than parallel interfaces. Also, it is easy to connect the ADC to the controller using a standard SPI.
Some of the newer ADCs have SPI, but some have non-standard 3- or 4-wire SPI as slaves because they want to achieve faster throughput rates. For example, the AD7616, AD7606, and AD7606B families have two or four SDO lines that provide faster throughput rates in serial mode. The AD7768, AD7779, and AD7134 families have multiple SDO lines that are used as SPI hosts. Users often encounter difficulties in designing microcontroller SPIs to configure ADCs and read**.
Figure 1The AD7768 is used as a serial master and has two data output pins (14001-193).
Interfaces with standard MCU SPI of ADCs
SPI is a synchronous, full-duplex, master-slave interface. Data from the master or slave is synchronized on the rising or falling edge of the clock. The master and slave can transmit data at the same time. Figure 2 shows a typical 4-wire MCU SPI interface connection.
Figure 2Interfaces with standard MCU SPI on ADC slaves.
To start SPI communication, the controller must send a clock signal and select the ADC by enabling the CS signal, which is usually an active-low signal. The SPI is a full-duplex interface, so the controller and ADC can output data simultaneously via the MOSI DIN and MISO DOUT lines, respectively. The controller SPI interface allows the user to flexibly select the rising or falling edge of the clock to sample and/or shift data. In order to reliably communicate between master and slave, the user must comply with the digital interface timing specifications of the microcontroller and ADC chip.
Figure 3An example of an SPI data clock timing diagram.
If the microcontroller SPI and ADC serial interfaces have a standard SPI timing mode, it is not a problem for the user to design PCB wiring and develop driver firmware. However, there are some new ADCs that have serial interface ports that are not typical of SPI timing modes. It does not appear to be possible for the MCU or DSP to read data through the AD7768 serial port, a non-standard time-series SPI port, as shown in Figure 4.
Figure 4AD7768 formatx=1 timing diagram, output via dout0 only.
This article describes how to manipulate a standard microcontroller SPI to interface with an ADC that has a non-standard SPI port.
In this article, we will give four solutions for reading ADC code through a serial interface
Solution 1: The MCU acts as an SPI slave and interfaces with the ADC as the SPI master via a DOUT line.
Solution 2: The MCU acts as an SPI slave and interfaces with the ADC as the SPI master through two DOUT lines.
Solution 3: The MCU acts as an SPI slave and interfaces with the ADC as the SPI master via DMA.
Solution 4: The MCU acts as an SPI master and SPI slave and reads data through two DOUT lines.
STM32F429 microcontroller SPI
Read the AD7768** via a DOUT line
As shown in Figure 4, when formatx=11 or 10, channels 0 to 7 output data only via dout0. In standard operating mode, the AD7768 The AD7768-4 operates as a host and data flows into the MCU, DSP, or FPGA. AD7768 The AD7768-4 provides data, a data clock (DCLK), and a falling-edge frame enable signal (DRDY) to the slave.
The STM32FXx family of microcontrollers is used in a wide range of applications. This MCU has multiple SPI ports that can be configured as an SPI master or slave using typical SPI timing modes. The methods described below can also be applied to other microcontrollers with 8-bit, 16-bit, or 32-bit frames.
The AD7768 and AD7768-4 are 8- and 4-channel simultaneous-sampling- ADCs with a - modulator and digital filter on each channel to support simultaneous sampling of AC and DC signals. These devices are at 110108dB dynamic range is achieved at a maximum input bandwidth of 8kHz with typical performance of 2ppm inl, 50 V bias error, and 30ppm gain error. AD7768 The AD7768-4 user can make trade-offs between input bandwidth, output data rate, and power consumption, and choose one of three power modes to optimize noise targeting and power consumption. AD7768 The flexibility of the AD7768-4 makes it a reusable platform for low power DC and high performance AC measurement modules. Unfortunately, the AD7768's serial interface is not a typical SPI timing mode, and the AD7768 acts as a serial interface host. In general, users must use FPGA CPLD as their controller. For example, the 32F429iDiscovery and AD7768 evaluation boards are used. The connection of the workaround SPI cable is shown in Figure 5. In this setup, all eight-channel data from the AD7768 is output via dout0 only.
Figure 5The AD7768 outputs data via DOUT0 to the STM32F429 MCU SPI connection.
Problems that need to be addressed:
The AD7768 is used as an SPI master, so the STM32F429i SPI must be configured as an SPI slave.
The DRDY high-level pulse only lasts one DCLK cycle, which is not typical of CS.
After all channels have finished outputting the data bits, the DCLK continues to output with the DRDY low.
Figure 6AD7768 data bit reads in a time series solution.
Solution 1: MCU SPI as a slave.
Interfaces with the SPI host ADC via a DOUT line.
Configure one SPI port on the STM32F429 (e.g. SPI4) as a slave to receive data bits on the MOSI at DCLK rate.
Connect the AD7768DRDY to the STM32F429 external interrupt input pins, Exti0, and NSS (SPI CS) pins. The rising edge of the DRDY will trigger the ExTi0 processing routine to enable the SPI slave to start receiving data bits on the first DCLK falling edge after the DRDY goes low. Timing design is crucial here.
Once all data from channels 0 to 7 has been received, SPI should be disabled to prevent reading additional invalid data, as DRDY will turn the SPI slave CS low and the DCLK will remain switched.
Precautions for MCU firmware development.
Figure 7Configure SPI4 peripherals.
When the software is in interrupt mode, the DCLK can run at up to 4 MHz to achieve an ODR of 8 kSps. The software should go into an interrupt handler to start the SPI within one and a half DCLK cycles (375 ns). To make it easier for the software to enter the interrupt routine, the MCU can read the data on the rising edge of the DCLK, providing an additional half of the DCLK cycle time. However, the T5 DCLK rises to a DOUTX invalid minimum of 3 ns (iovdd = 1.).4 ns at 8 V), hence the propagation delay (>|) on DOUTXt5|+MCU hold time) should be increased by PCB routing or buffering.
Solution 2: MCU SPI as a slave.
Interfaces with the SPI host ADC via two DOUT lines.
In the first solution, only dout0 is used to output all 8 channels of data. As a result, data reads limit the ADC throughput rate to 8 ksps. As shown in Figure 1, the data transfer time can be reduced by outputting channels 0 to 3 on dout0 and 4 to 7 on dout1. The connection of the serial cable is shown in Figure 7. With this improvement, the ODR can easily reach 4 KSPS at 16 MHz DCLK.
Figure 8The AD7768 outputs data via DOUT0 and DOUT1 to the STM32F429 MCU SPI connection.
Instead of interrupt mode, the firmware can use polling mode to reduce the time delay from the DRDY rising edge trigger to enabling the SPI to receive the data. This allows for an ODR of 32ksps at 8MHz DCLK.
Figure 9exti0 is in polling mode, and SPI4 and SPI5 receive AD7768 data bits via DOUT0 and DOUT1.
Solution 3: MCU SPI as a slave.
Interface with SPI host ADC via DMA.
Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory, as well as between memory and memory. DMA can move data quickly without the need for any MCU operations, freeing up MCU resources for other operations. The following is a design description for the MCU SPI to be used as a slave to receive data via DMA.
Figure 10Exti0 is in polling mode and the SPI4 DMA receives the AD7768 data bit via DOUT0.
Solution 4: MCU SPI as master and slave.
The data is read through two DOUT lines.
High-throughput or multi-channel precision ADCs provide two, four, or even eight SDO lines for SPI ports for faster read** in serial mode. For microcontrollers with two or more SPI ports, these SPI ports can be operated simultaneously to speed up reads.
In the following use case, the 32F429iDiscovery uses SPI4 as the SPI master and SPI5 as the SPI slave to receive the EVAL-AD7606B-FMCZ data via Douta and DOUTB, as shown in Figure 8.
The AD7606B is a 16-bit, simultaneous-sampling, analog-to-digital conversion data acquisition system (DAS) with eight channels, each containing analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter, and a 16-bit successive approximation register (SAR) ADC.
The AD7606B also has a built-in flexible digital filter and low drift25V precision voltage reference and reference buffer to drive ADCs and flexible parallel and serial interfaces. The AD7606B operates from a single 5V supply and supports 10V, 5V, and 2The 5V true bipolar input range enables all channels to sample at a throughput rate of 800 kSps.
Figure 11In master-slave mode, the MCU SPI is used to receive data via Douta and DOUTB.
Figure 12SPI4 is configured as the master and SPI5 is configured as the slave.
Figure 13 shows a screenshot of the AD7606B's digital interfaces for busy, sclk, douta, and doub running at 240ksps.
Figure 13Oscilloscope screenshot of the AD7606B Busy, SCLK, and data on Douta and Doutb.
Summary
This article discusses how to use a microcontroller SPI to access an ADC with a non-standard SPI interface. These methods can be used directly or with minor adjustments to control the ADC SPIIt can be used as an SPI host or with multiple DOUT lines to increase throughput.
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