As foundries develop increasingly advanced process nodes to meet consumer demand, the number of transistors on today's advanced processors reaches tens of billions, a far cry from the mid-1970s when there were only a few thousand transistors.
The most far-reaching technology that has impacted the semiconductor industry over the past few decades has been the steady development of transistors. In semiconductor manufacturing, each new generation brings about an increase in transistor density, and in recent years, we have been able to hear: "Moore's Law cannot be continued, and the infinitesimal limit of transistors is coming." Voices like that.
At the recent IEEE International Electronic Equipment Conference, Intel, Samsung, and TSMC all demonstrated their latest technologies. Among them, CFETS (Complementary Field Effect Transistor) invariably appeared. It can be said that CFET has been included in the next development plan of the chip roadmap. In this article, we'll take a look at the latest CFET progress revealed by the latest Big Three, and why CFTs are crazy.
Towards CFET, towards verticalization
In semiconductor manufacturing, each new generation brings about an increase in transistor density. However, this is not achieved by reducing the feature size, but by reducing the number of features per transistor. When the transistor can't get smaller, the only direction is upward.
To understand what problems CFEts solve, let's first look at the evolution of transistors.
In the earliest days of transistors, conventional transistors were planar fets, which were formed by placing gate electrodes at the top of the channel region, effectively allowing the device to conduct electricity in a two-dimensional plane. However, if the gate length is less than 20 nm, the source and drain are too close together and the oxide is thinner, which is likely to leak current, making it difficult to further reduce the size of the transistor.
In 2011, Intel stepped up. Pioneered the use of FinFETs (FinFET (Fin-Effect Transistors) at the 22nm technology node. FinFET has achieved two breakthroughs, the first is to make the crystal thinner and solve the problem of leakage, and the second is to develop upward, and the internal structure of the wafer has changed from horizontal to vertical.
The evolution of CMOS.
As you can see from the diagram above, from Planar FET to FinFET, the transistor is "erected". This structural change has been very effective, with power consumption reduced by approximately 50% and performance improved by 37% at the same performance level as the previous generation planar architecture.
As semiconductor processes continue to advance, FinFETs are expected to improve performance and reduce area in accordance with Moore's Law. However, when it comes to 7nm and 5nm, FinFETs are no longer enough. At 5nm, even with the use of EUV lithography technology, it is becoming more and more difficult to reduce the size of chips based on the FinFET structure.
Later, the industry proposed GAAFET (Surround Gate Field Effect Transistor), which is also an upward direction. Essentially, GAAFET is the fins of the FinFET that are rotated 90° and stacked upwards to increase the contact area between the gate and the channel.
With the advent of Gaafet, transistors have been able to move forward for several more generations. However, there will still be problems, because the capabilities of the GAA transistor architecture have their limitations, and the optimization of the structure form of a single device has been pushed to the limit.
That's when CFETS came out and continued to move upward. In the CFET architecture, N and PMOS devices are stacked on top of each other, and the size limit of the traditional N P-FET coplanar layout spacing can be scaled down to 4-T (track) height in the logic standard cell in the circuit, while reducing the SRAM cell area by more than 40%.
After 1nm, CFETS became the successors to GAA. This year, Intel, TSMC, and Samsung have all demonstrated their own CFET technology, but this technology was proposed 20 years ago, Dr. Zhang Shengdong of Peking University has proposed the concept of stacked complementary transistors (stacked CMOS), and the prototype of stacked transistors was developed in 2004.
Dr. Shengdong Zhang also published "A Stacked CMOS Technology on SOI Substrate" in IEEE Electron Device Letters ( Volume: 25, Issue: 9, September 2004, P661-663).
This ** has been cited in relevant reports of Intel and TSMC. TSMC pointed out in the VLSI 2021 report "CMOS Device Technology for the Next Decade" that Peking University's 3D stacked CMOS transistor is the industry's first stacked complementary transistor, 15 years before TSMC and Intel.
The mystery of CFET?
As mentioned earlier, CFET architectures must be stacked vertically with NMOS and PMOS, which makes the process more complex. At present, there are two ways to implement CFETs in the industry: monolithic and sequential.
The monolithic CFET flow is divided into three parts: epitaxial growth of the bottom channel, deposition of the middle layer, and epitaxial growth of the top channel. The advantage of monolithic is that CFETS can be introduced quickly, and this integration solution is minimally disruptive and costly compared to existing nanochip-based processes.
Sequential is the manufacture of components from the bottom up, using wafer bonding technology to cover the top with a semiconductor layer, integrate the top components, and connect the top and bottom grids. Although the sequential integration process is relatively simple, wafer transfer is difficult. Therefore, there is no clear conclusion in the industry as to which of the two ways to choose.
At present, IMEC is also engaged in CFET research in the world. IMEC's manufacturing roadmap shows that FinFET transistors will reach the end of 3nm and then switch to Gate All Around (GAA) technology transistors, with mass production in 2024, followed by FSFETs and CFETS.
In 2020, IMEC showcased a CFET device with a gate pitch (i.e., contact polycrystalline pitch (CPP)) of 90nm, and in 2023, IMEC showcased a monopole CFET device built with an industry-relevant gate pitch of 48 nm through monolithic integration.
A) End of Process Cross-Section **IMEC for Bottom PFET and (B) Top NFET (LG, Phys=27nm).
The battle between the three giants of CFET
With all that said, let's take a look at the details of TSMC, Intel, and Samsung's CFETs.
TSMC has revealed the news about CFETS at several technical seminars, and said that the laboratory already has available CFETS internally.
Recently, TSMC released its latest ** titled "48nm Gate Spacing Complementary Field Effect Transistor (CFET) Demonstration for Future Logic Technology Expansion", which once again demonstrated its interest in CFET.
The TSMC team will discuss what they describe as a practical monolithic CFET approach for logic technology scaling at 48 nm gate pitch. Like Intel, they use n-type nanosheet transistors on top of p-type nanosheet transistors. This will report on-state current and subthreshold leakage – described as "high" and "low" respectively in the summary. This results in an on/off current ratio of six orders of magnitude.
TSMC CFET with cross-sectional transmission electron microscopy** shows TSMC's monolithic CFETs with a gate spacing of 48 nm, with the NFET placed above the PFET, and both types of transistors surrounded by a single metal gate. **iedm
According to the abstract, the transistor has a FET yield of more than 90% and successfully passed the test. The final comment in the synopsis reads: "While other essential functions must still be integrated to unlock the potential of CFET technology, this work paves the way to achieve this." ”
Intel was the first of the three companies to demonstrate a CFET, showing an early version of the CFET in 2020. Again, the P-channel and N-channel transistors are stacked on top of each other to reduce the footprint of the CMOS pair.
Cross-section of an Intel stacked nanoribbon transistor, 2020.
In that year's study, the combined transistor provided a subthreshold slope of less than 75 mV ten octaves, as well as a drain induction barrier reduction factor of less than 30 mV for gates longer than 30 nm. Although the gate in this work is relatively large, the Intel team expects to significantly reduce the cell size by self-aligning the stack.
In May this year, Intel announced the key technology roadmap, and the "stacked CFET MOSFET architecture" once again appeared. In its presentation, the CFET design can allow eight nanosheets to be stacked for use with RibbonFETs, thereby increasing transistor density.
Recently, Intel showed off one of the simplest circuits made using CFETS, with several improvements for inverters. The CMOS inverter sends the same input voltage to the grid of both devices in the stack and produces an output that is logically opposite to the input, and the inverter does so on one fin. Intel describes it as: the industry's first full-featured inverter test circuit in a CFET, built with 60nm gate pitch.
The transistors on display this time have three major characteristics: first, denser circuitry. 60 nm gate spacing, which indicates a highly compact design that enables the creation of denser circuits. Second, vertical stacking. Vertically stacked dual-source drain epitaxy improves space efficiency. In addition, it uses bimetallic work function gate stacking. This vertical stacking minimizes interconnect latency and improves overall efficiency. Thirdly, the power transmission on the back. Transistors use direct device contact for backside power delivery, which significantly contributes to device performance and heat dissipation.
Samsung refers to its CFEs as "3DSFETs" or 3D stacked FETs. Currently, Samsung's 3DSFET structure has been selected as the next-generation GAA technology and has begun full-scale commercial development.
Samsung's latest results, like TSMC, have managed to control the gate spacing at 48nm, and features of its CFET solution include a new way to form a dielectric layer between the top and bottom transistors to maintain the spacing. Samsung has succeeded in solving the problem of source leakage of galvanically isolated stacked N-type and P-type MOS components by replacing traditional wet etching with a new type of dry etching with wet chemicals.
Conclusion
CFETs are a revolutionary device that has the potential to be the ultimate device for scaled down CMOS. However, CFET technology research is just the beginning, and there is still a lot of work to be done before it is ready.
The industry has been using FinFETs for five generations, more than 10 years, and then GAA arrived. Then the next generation of GAAFET may also be used for several years, at least a few generations. As TSMC said, it will take generations for new CFET transistors to materialize.