Review and prospect of silicon carbide device packaging progress
Du Zechen, Zhang Yijie, Zhang Wenting, An Yunlai, Tang Xinling, Du Yujie, Yang Fei, Wu Junmin.
State Key Laboratory of Advanced Power Transmission Technology of Global Energy Interconnection Research Institute).
Abstract:Silicon carbide (SiC) has the advantages of forbidden bandwidth, strong critical breakdown field, high thermal conductivity, high pressure, high temperature, and high frequency. The traditional packaging method applied to silicon-based devices has large parasitic inductance parameters, which is difficult to match the fast switching characteristics of SiC devices, and the packaging reliability is greatly reduced under high temperature conditions, so it is necessary to improve the existing packaging technology in order to give full play to the advantages of SiC devices. In view of the above challenges, the existing low-parasitic inductance packaging methods at home and abroad are summarized. This paper analyzes the existing high-temperature packaging technology, and summarizes and prospects the packaging technology of SiC devices in combination with the development trend of new energy power system.
1 Introduction. As China's energy proportion and energy consumption mode have shifted from fossil energy to clean energy such as electricity and hydrogen energy, in September 2020, President ** announced at the United Nations General Assembly that China will adopt more powerful policies and measures, strive to peak carbon dioxide emissions before 2030, and strive to achieve carbon neutrality before 2060. In March 2021, the ninth meeting of the Finance and Economics Committee proposed to build a new power system with new energy as the main body.
Silicon carbide (SiC) forbidden bandwidth, strong critical breakdown field, high thermal conductivity, is a typical representative of the third generation of semiconductors, SiC materials, devices have been included in the national "14th Five-Year Plan" science and technology plan, it has the advantages of high voltage, low loss, high temperature resistance and other advantages, for the power electronic equipment efficiency, miniaturization has an important role.
These excellent characteristics of SiC materials need to be packaged to achieve efficient and reliable connection between power and signal, so that they can be perfectly demonstrated in power electronic equipment, while traditional silicon-based device packaging technology faces problems such as high parasitic inductance and performance degradation at high temperature when applied to SiC devices. In this paper, several low-parasitic inductance packaging technologies and high-temperature packaging technologies are summarized, and the development of SiC devices in new energy power systems is analyzed and prospected.
2 Low parasitic inductance packaging technology.
2.1 Chip stress-free package.
In order to reduce the parasitic inductance of the high-voltage SiC module and eliminate the stress on the surface of the chip, the Global Energy Interconnection Research Institute proposed a ZPOC (Zero Pressure on Chip) package structure with extremely low parasitic inductance, and the schematic diagram of the ZPOC package is shown in Figure 1Subsequently, the Joint Research Institute adopted the ZPOC package structure, based on forward parameter matching and chip paralleling, and developed 65 kV 100 A SIC SBD device;Combined with the SiC SBD series connection technology, 6 devices were connected in series, and the 39 kV 100 A SiC SBD was developed
components and found their applications in 24 kV converter valve power modules.
The module using ZPOC packaging technology uses a combination of soldering and crimping in the packaging form, which has the advantages of double-sided heat dissipation, easy series connection, electromagnetic compatibility, etc., which can effectively reduce the parasitic inductance introduced by the module in the packaging process, and the parasitic inductance of the package is measured by experiments to be 356 nH, which offers significant advantages for improving the switching characteristics of the module.
2.2 Three-dimensional (3D) package.
The 3D package (Fig. 2) technology superimposes the upper arm of the SiC module directly on the lower arm, and the upper and lower arms can be superimposed to reduce the connection line at the midpoint of the bridge arm (see Figure 3), and the parasitic inductance of the module can be reduced to less than 1 nh.
In 2010, the Grenoble electrical engineering laboratory Vagnon [9] built a single-phase 400 V 40 A high-frequency (HF) rectifier and buck converter module using 3D packaging technology. The experimental results show that the IGBT has only 10% voltage overshoot when it is turned off, and there is almost no undervoltage when it is turned on. As a result, 3D packaging technology can virtually eliminate the common source inductance, while the common mode current is well suppressed.
In 2015, Regnat [10] at the European R&D Center proposed a new 3D package based on printed circuit board (PCB) embedded chip technology. Utilizing PCOC (Power on Chip) technology, the SiC MOSFET chip is embedded inside the PCB to achieve a lower inductance path and common-mode capacitance.
The module shown in Figure 4 has a 30 mm 30 mm 2 mm thick PCB with a 105 m copper surface and 16 decoupling capacitors on the edge of the module. To model the commutation unit in the switching state during the impedance measurement, a short circuit was implemented between the plus and minus ends of the unfilled chip position vias in the front and rear rings. The measuring connectors are located on two free edges, so that the front commutation loop and the rear commutation Lope impedance can be measured by simply reversing the module. The measured power loop inductance of the front ring is 023 nh with an inductance of 0 in the rear ring21 nH, so PCOC modules with embedded chip technology enable compact, high-density power modules with significantly reduced parasitic inductance in the loop, making them suitable for wide bandgap semiconductor devices (e.g., SiCs) with fast turn-on and turn-off times.
3D packaging technology eliminates bond wires in the module, which can effectively improve the power density of the device and take full advantage of the high frequency of the SiC device. At the same time, the use of 3D packaging technology can reduce the parasitic inductance value of the loop and reduce the size of the module, thereby promoting the power electronics to high frequency, high efficiency, and high power density.
2.3 DBC+PCB hybrid package.
Conventional solder-type module packages use direct bonded copper (DBC) plates, and the chips can only be laid out on the surface, and the large current loop area makes it very difficult to reduce the parasitic inductance of the module. Therefore, CPES, Huazhong University of Science and Technology, etc. combine the DBC process with the PCB board, and lead it to the PCB board through the connection of the bonding wire on the chip, so that the control commutation loop can be directly realized between the PCB layers, and the parasitic inductance parameters can be reduced by reducing the current loop of the module.
Zheng Chen et al. from Virginia Tech used a cross-sectional structure of a hybrid DBC+PCB package as shown in Figure 5, using a multilayer PCB instead of the original polyimide-copper. The semiconductor chip is embedded by cutting the PCB so that both the PCB and the device can be connected to the same DBC substrate, and then the top electrode of the device is connected to the top copper bar on the PCB using a bonding wire.
Compared to traditional processes, DBC+PCB hybrid packages offer a number of advantages. 1) The PCB layer of the package can be soldered to the substrate with the semiconductor chip in a single reflow process, which greatly simplifies the manufacturing process of hybrid modules. 2) By increasing the copper layer of the board and using through-holes, blind vias, and even buried vias, more complex routing can be implemented on the PCB, allowing the switching current path to be more flexibly controlled, while providing the possibility of embedding gate driver circuitry in the module. 3) Hybrid packaging technology reduces parasitic inductance parameters by reducing the area of the current loop. The parasitic inductance of the hybrid module is only 10% to 20% of that of the discrete TO-247 package. At the same time, the loop inductance is reduced by 35% and the module volume is reduced by about 40% compared to conventional wire bonding modules.
Zhizhao Huang of Huazhong University of Science and Technology designed a hybrid module shown in Figure 6, which includes an ALN ceramic substrate, FPC, and SiC chips. The chip is soldered to the underlying DBC through a window on the FPC to improve heat dissipationThe chip and FPC are soldered to the DBC at the same time, and the upper surface electrodes of the chip are connected to the FPC through bonding wires, and the upper and lower layers of copper foil of the FPC are connected through vias. Since the conductors through which the commutation loop passes exist in different conductor layers of the FPC, and the current flows in opposite directions, a mutual inductance cancellation loop is formedEnhanced mutual inductance with thin FPCs greatly reduces parasitic inductance in the main circuit.
The hybrid module passes through the impedance test results of the downtube commutation circuit, from which the total inductance of the main circuit is calculated to be 38 nh。The DU dt for simultaneous turn-off is 3738 V ns and 3765 V ns, demonstrating that the use of a hybrid DBC+PCB package technology reduces the parasitic and common inductance of the module drive loop.
Both hybrid package formats can effectively reduce the parasitic inductance parameters of the module and improve the heat dissipation capacity of the module.
2.4 Flip-chip package for a single chip.
Most of the commercially available SiC power chips are vertically typed, so based on BGA's packaging technology, the SEAL team at the University of Arkansas proposed a flip-chip packaging technology suitable for a single chip, in which the electrodes on the back of the chip are flipped to the same plane as the front electrodes of the chip through metal connectors, and the electrodes are fixed with solder (see Figure 7).
The flip-chip package eliminates the need for bonding wires and power terminals, which can effectively reduce the size of the module, thereby reducing the material cost in the package. Compared to the commonly used TO-247 package, the volume of this package is reduced to 702%, and the on-resistance is reduced by 24%.
2.5 Flexible PCB+ double-sided sintered hybrid package.
Double-sided sintering technology offers higher reliability than traditional die soldering and wire bonding components. Semikron's KASKO assembled a system with extremely low inductance (1.) through adjustments to gate and source pad layout, gate pad position and isolation, gate resistance, and chip metallization, as shown in Figure 84 nH).
The parasitic inductance between the DBC of the chip and the flexible foil in the hybrid package module is 0At 45 nh, the parasitic inductance between the connection of the flexible foil to the DC bus with coil spring is 085 nh。
The flexible PCB+ double-sided sintered hybrid package offers a 91% reduction in total parasitic inductance compared to conventional modules of the same power class3%。In terms of dynamic characteristics, the DU DT and DI DT during the turn-off of the hybrid package module are 53 kV s and 67 kS respectively. At the same time, the total switching losses of the hybrid package module are only 20% of that of the IGBT module compared to a 62 mm IGBT module of the same power class.
2.6 Planar interconnect technology.
To reduce the on-resistance and parasitic inductance of the device, Siemens has developed the Siemens Planar Interconnect Technology (SIPLIT) [20]. An SIC device with planar interconnect technology is shown in Figure 9.
Compared to wire bonding, planar interconnect technology has a chip contact area of up to 90% and provides a larger cross-section. As a result, the packaging resistance of chips with planar interconnect technology is reduced by 25%;In addition, the coplanar structure of the interconnect covers only a small area of the current loop compared to the loop spanned by wire bonding, resulting in a 50% reduction in parasitic inductance on the interconnect. SIPLIT technology overcomes the performance and reliability limitations of thick aluminum wire bonding. Experimental results show that this technology can effectively reduce the resistance, inductance, and thermal resistance in the package, and effectively improve the EMI performance.
3 High temperature packaging technology.
3.1 Double-sided heat dissipation technology.
The double-sided packaging process achieves better heat dissipation by soldering the DBC board on both the upper and lower surfaces of the module chip, or using silver sintering technology to solder one side of the chip to the DBC and connect the aluminum sheet on the other side. Double-sided packaging technology can not only improve the field strength distribution at the edge of the circuit board, but also reduce the parasitic capacitance to the ground at the midpoint of EMI and bridge arm, so it has a strong application demand in the module inside the new energy electric vehicle.
Wang Yangang et al. of Zhuzhou CRRC have developed a 650 V 600 A SiC half-bridge DSC automotive power module with double-sided cooling, which bonds both sides of the power chip to a flat part with isolation ability, the metal gasket is directly bonded to the top of the chip, and the bonding interface is formed by soldering or silver sintering process. Compared to single-sided cooled baseplate-less modules, the thermal resistance is reduced by 30%.
Yang et al. of the University of Tennessee designed a low-parasitic inductance SiC power module with double-sided heat dissipation (shown in Figure 10) with an island substrate layout with a power loop inductance of 659 nh reduced to 26 NH, a decrease of more than 60%.
Cree's Liang designed a double-sided cooling module like the one shown in Figure 11, with two cold plates (chillers) bonded directly to the outside of these substrates, allowing the module to integrate heat dissipation on both sides. Power switches with a phase-bridged electrical topology are configured with a face-up, face-down interconnect. This module reduces the losses associated with these parasitic effects by up to 75% compared to conventional modules, and reduces the specific thermal resistivity to 033 cm2·w, a 38% reduction compared to conventional modules. The current density of the module reaches 220A cm2, which is 1 of conventional modules52 times.
Compared with traditional packages, the advantage of double-sided heat dissipation technology is that it can effectively reduce the thermal resistance of the module, thereby improving the heat dissipation capacity and current density of the moduleIn addition, it can effectively reduce the volume of heat dissipation components in the system and improve the overall power density of the system.
3.2 Low-pressure sintering process + copper wire bonding technology.
The high-temperature characteristics of SiC bring many benefits but also put forward new requirements for packaging materials and processes. Danfoss' Haumann has proposed a low-pressure sintering process for chip bonding, which is achieved through three innovative solutions: metallization, top-attached metal buffers (Danfoss bonding buffer DBB) and copper wire bonding. The low-pressure sintering process involves the application of silver paste between the connecting parts, followed by the application of pressure to create a stable connection between the dense silver layer and the connecting parts (e.g. DCB substrates).Second, copper wire bonding increases current capacity by 37%. The power cycling capability of the 400 V 150 A module with this technology has been increased by 15 times to 600,000 cycles, which greatly improves the reliability of the module.
At present, solder chips or solder paste are commonly used as the connecting agent between chips and DBC boards, and their processes are mature and simple, but the thermal conductivity of solder is low and will change with temperature, and the applicability to SiC devices under high temperature conditions is poor, and the reliability of the solder layer is easy to cause module failure. Boettge uses sintered silver bonding (LTJT) and transient liquid phase soldering (TLPS) techniques to effectively reduce the voiding rate of the solder layer.
The high-temperature packaging technology adopts copper wire bonding technology, LTJT and TLPS technology, which effectively improves the current capacity of the module and reduces the voiding rate of the solder layer, thereby effectively improving the reliability of the module under various high-temperature working conditions.
4 Summary of new packaging structure and high-temperature packaging technology.
By analyzing the above new packaging structures and high-temperature packaging technologies with low parasitic inductance, it can be found that although the high-speed switching characteristics of SiC power devices achieve high controllability and low switching loss (i.e., high conversion efficiency) of new power electronic equipment, the realization of high switching speed depends on new technologies such as low-inductance wiring. The technical characteristics and advantages of the eight technologies are shown in Table 1.
As can be seen from Table 1, the inductance of the module can be reduced by the inert packaging of the module by the reactive packaging of the D package, the hybrid packaging of DBC+PCB, the hybrid packaging of flexible PCB+ double-sided sintering, and the planar interconnect technologyAmong them, the flexible PCB+ double-sided sintered hybrid packaging technology has the largest reduction in parasitic inductance, reaching 913%；Both planar interconnect technology and reverse chip packaging technology can reduce the on-resistance by about 25%, and the double-sided heat dissipation technology can reduce the thermal resistance by about 30%.
5 Challenges and Prospects of SiC Packaging.
As China begins to build a new power system with new energy as the main body, power electronic equipment needs to play a key supporting role at all levels of the power system, and the application of SIC devices will greatly promote the process of flexible semiconductorization of the power grid, and the application of SIC devices in the new power system has broad prospects. In the foreseeable future, power electronics will develop rapidly in the direction of high frequency, high efficiency, and high power density.
In the field of power system, with the growing demand for high-voltage and high-current SiC devices, the industry has also put forward higher requirements for the parasitic inductance, on-resistance, switching loss, thermal resistance and other parameters of the module. With the increase in the market share of modules based on wide bandgap semiconductor materials such as SICs, the new packaging technologies in the future will focus on reducing the parasitic inductance of the module and improving the high-temperature reliability of the module.