During wafer processing, thinning, grinding, and polishing sequentially remove the damaged layer introduced by the slice, resulting in a global planarization of the wafer, resulting in a damage-free, low-surface roughness 4H-SiC wafer. However, the processing process of 4H-SiC wafers suffers from incomplete removal of process damage or the inevitable introduction of new damage. According to whether the damage is visible under optical microscopy, the damage on the surface of 4H-SiC wafers is divided into surface damage (SDS) and subsurface damage (SSDS). Among them, SDS includes scratches, bumps, pits, etc., which can be directly observed by an optical microscopeSSDs, on the other hand, are mainly distributed below the surface and cannot be directly observed by optical microscopy.
SSDs of 4H-SiC wafers have been discovered to include subsurface microcracks, dislocation aggregation, amorphous phases, and residual stresses. SDS SSDS will act as the nucleation center of the defect in the subsequent epitaxial process, which will seriously affect the quality of the epitaxial layer, which in turn will affect the performance and reliability of 4H-SiC-based devices. Therefore, accurate identification and removal of SDS SSDs is critical for the processing and application of high-quality 4H-SiC wafers.
The main processing processes of 4H-SiC wafers are divided into: slicing, thinning, grinding, polishing and cleaning. In addition to the quality problems of the crystal itself (such as carbon encapsulation, polytypes, microtubules, dislocations, etc.), the defect that has the greatest impact on substrate epitaxy and subsequent device manufacturing is SDS SSDS. Since both originate from wafer processing, it is of great significance to clarify the generation and removal mechanism of SDS SSDs and optimize the wafer processing process to strictly control the SDS SSDs of 4HSiC wafers and improve the quality of subsequent 4H-SiC single crystal growth or homogeneous epitaxy.
In processes such as slicing of 4H-SiC, the material is mainly removed by a brittle fracture mode, which inevitably introduces microcracks below the surface, resulting in SDS and SSDS of the material. Microcracks on the subsurface not only reduce the mechanical strength of 4H-SiC wafers, but also affect the subsequent process and production costs, which is an important indicator to evaluate the quality of wafer processing.
The slicing process is a key factor affecting the thickness of the microcrack damage layer during the slicing process. During the subsequent thinning, grinding and polishing process, the thickness of the damaged layer is gradually reduced and effectively removed after polishing to obtain a globally flat, near-lossless 4H-SiC wafer.
The results of nanoindentation test show that the damaged layer generated by 4H-SiC under mechanical stress shows Y-shaped cracks on the macroscopic level, including median cracks and lateral cracks. Among them, the median crack occurs during the abrasive loading process, and with the increase of the abrasive indentation depth, the median crack starts from the bottom of the deformation zone and expands downwardWhen unloading, the median crack gradually closes, and the lateral crack starts from the bottom of the deformation zone and spreads to both sides and surface, and when the lateral crack expands to the surface, surface fragmentation is formed. Semiconductors