Welcome to today's podcast, I'm your friend, a veteran tech writer who walks around randomly!In this information** era, AI technology is developing at an astonishing speed, and the heart of AI, the chip architecture, is undergoing unprecedented changes. Today, we're going to explore this story togetherDynamic vs. Static Graphs, Efficiency vs. Performanceof profound change.
Recently, an interesting statistic caught my attention: in the new generation of AI chips,Dataflow schemabecame mainstream. These chips, such as Tesla Dojo and Tenstorren Grayskull, are implemented in different ways, but they all have one thing in common:Graph-level scheduled execution
Unlike traditional GPUs that use the kernel by kernel execution mode, the DataFlow architecture uses data flow graphs to execute and scheduleSIMD architecturewithHigh-speed interconnection and large bandwidthThese designs clearly have far-reaching considerations, such as energy efficiency and scalability.
However, the DataFlow architecture presents a great challenge for the software:
Programming difficulty:simd complicates schedule, tilling, and vectorization tensorization.
Performance optimization: The independent optimization of the layer and operator layer cannot maximize the chip performance, and the optimization needs to be fused.
Difficult to debug: Debugging and positioning problems caused by the sinking of the whole image.
Dynamic support: Control flow and dynamic shape are big challenges for DataFlow architectures.
The DataFlow architecture may be inherently more suitableStatic diagram mode, to strengthen the dynamic shape and control flow capabilities, is a deepening on the static graph. If you choose a dynamic graph, you may not even have the opportunity to play the performance of these chips. However, developers have started to enjoy the convenience of dynamic graphs.
So, here's the problem:How to balance the performance of static graphs with the convenience of dynamic graphs
The research and industry needs in the AI field are different, and static graphs are conducive to the parallel computing power and scale, while dynamic graphs are conducive to improving development efficiency. The challenge and opportunity we face is how to achieve itThe combination of movement and static, or even the unity of movement and static。In this process, the future is still full of uncertainty as to who will dominate the static and dynamic graphs. But uncertainty, for the development of new frameworks, is always a good thing.
Thank you all for listening!I'm Li Ming, and I hope today's sharing can give you a deeper understanding of the transformation of AI chip architecture. The future of AI is constantly evolving, and we will continue to explore and think about it. Don't forget to subscribe to our podcast for the next episode, where we will bring you more exciting content on the cutting edge of technology. See you soon!