From 7nm to 5nm, from 5nm to 3nm, the semiconductor industry's pursuit of advanced processes never stops. In 2022, when TSMC announced that it had successfully mastered the process technology of mass mass production of 3nm fin-effect transistors, 1nm began to approach step by step.
The mastery of advanced technology means higher performance and more cutting-edge technology. Leapfrogging from 3nm to 1nm is a huge challenge. Therefore, 1nm is also full of ** for the industry.
1nm, never forget
The R&D and production of process manufacturing require a lot of resources, on the one hand, technology accumulation, such as transistor architecture, material selection, manufacturing process, etc., all need to solve problems;On the other hand, strong capital, talent and equipment are also needed, and it is known that from 5nm to 3nm, production costs have also doubled. Not everyone is "qualified" to pursue 1nm. The gap between skipping from 28nm to 1nm is absolutely prohibitive.
Let's take a look at the institutions and companies that are currently ambitious to pursue 1nm.
The latest news is that Japan plans to cooperate with France to develop 1nm process semiconductors. Specifically, Japanese chip manufacturer Rapidus and the University of Tokyo will collaborate with LETI, a French semiconductor research institute, to jointly develop the basic technology for next-generation semiconductor designs with a wire width of 1 nm.
CEA-Leti in France was founded in 1967 as the Department of Electronics at CENG (Centre for Nuclear Research in Grenoble), founded in 1957. CEA-LETI has also achieved many important milestones in the development of chips, such as being one of the key promoters of Insulator-on-Silicon Field Effect Transistor (FD-SOI) technology.
Japanese chipmaker Rapidus should be familiar to everyone. The company was founded very late – in August 2022, it brought together 8 Japanese companies and 70 billion yen in funding from Japan**. The goal of the establishment is to mass produce 2nm chips within 4 years. At that time, it established a strategic partnership with IBM and moved towards 2nm. However, at present, the most advanced process in Japan is still stuck at 45nm. Therefore, whether Japan can pass this "big gamble" and leap from 45nm to 2nm is something that the industry is still looking forward to.
It now seems that Japan's ambitions are not limited to 2nm, but also to 1nm. The cooperation is based on the exchange of personnel and basic research with the University of Tokyo and the Leti Research Institute. Leti will explore new transistor structures, while Rapidus and other Japanese partners will send scientists who will then evaluate and test prototypes.
IBM launched the world's first 2nm chip in 2021, using GAA surround gate transistor technology, which shook the industry for a while. Historically, it took IBM less than four years to go from 5nm to 2nm. After 2nm, IBM naturally moved towards 1nm. At the IEDM conference in late 2022, IBM showcased its technology ready for the transition to 1nm and beyond: Interconnect 30 and VTFETs.
In May this year, imec unveiled a roadmap for transistors below 1nm, in which 1nm equals 10 angstroms. Not only that, but in June, IMEC said that it had signed an important agreement with ASML to jointly develop sub-1nm chips with ASML. ASML will offer the latest model 0The Twinscan exe that is key to 55 Na EUV, 2nm and 1nm process development: 5200, and the latest model 033 na euv twinscan nxe:3800。
In terms of enterprises, as the only wafer factory that can successfully achieve 3nm mass production, TSMC also began to study 1nm early. TSMC has selected the location of its new 1nm fab, which is in the Zhuke Longtan Park. From the perspective of progress, if everything goes well, the third phase of Zhuke Longtan Park will be available for manufacturers to start factory construction operations in mid-2026, which also means that TSMC's 1nm factory can start construction in 2026 at the earliest, trial production in 2027, and mass production in 2028. In fact, this is also in line with imec**'s sub-1nm roadmap.
*：imec
Chip leader Intel is also irresistible to 1nm. From the point of view of process nodes, Intel is currently preparing to use Intel 4, for Meteor Lake processors and Granite Rapids, and the next step will be Intel 3, which will use EUV lithography for greater modularity, with PPW increasing to 18%. And Intel's latest processes are 20A and 18A. The Intel 20A was originally called Intel 1, but it was named the 20A because Intel wanted to "better evoke the next era of innovation".
Now the question arises: how to achieve the 1nm future?
2D material
The search for the right transistor structure as well as the right transistor material to achieve the 1nm process geometry is still a good direction. The use of non-silicon materials facilitates the fabrication of very tiny transistors – as small as 1 nanometer.
In 2019, IMEC demonstrated at the IEEE conference that 2D materials can achieve process nodes below 1nm. At that time, IMEC had already demonstrated that molybdenum disulfide (MOS2) MOSFETs with tiny feature sizes could open the way for extreme scaling of transistors, well below the level of the short-channel effect of silicon devices.
MOS2 is a two-dimensional material, which means that it can grow in a stable form, with a thickness of just one atom and, most importantly, atomic precision at that scale.
Researchers at MIT, Nanyang Technological University, and TSMC have found that two-dimensional materials combined with semi-metallic bismuth (BI) can achieve extremely low resistance, overcoming the challenge of realizing 1-nanometer chips.
TSMC also announced that it has made a breakthrough in 2D materials, approaching 1 nm. In 2022, TSMC, Massachusetts Institute of Technology, and Nanyang Technological University jointly published a paper describing the manufacturing challenges posed by metal-induced conductive gaps and how single-layer technologies are affected by these metal-induced gaps.
In this article, it is proposed to use post-transition metal bismuth and some semiconductor monolayer transition metal dichalcogenides to reduce the size of the gap, resulting in the production of 2D transistors that are much smaller than before. In the experiment, TSMC tried a variety of current low-resistance semiconductor materials, molybdenum disulfide (MOS2), tungsten disulfide (WS2) and tungsten diselenide (WSE2).
Alter copper (Cu) interconnects
In computer chips, the wiring between semiconductor components is called an interconnect. To put it simply, an interconnect is the way of current flowing between the transistors, memories, processing units, and other components of a chip, and the more efficiently the interconnect is transmitted, the more efficient the chip will be.
Prior to 1997, aluminum interconnects were often used. Since then, IBM has discovered more efficient copper interconnects. The conductivity of copper wire is about 40% lower than that of aluminum wire, which means that the processing speed is about 15% higher. Over the past few decades, this dramatic shift has led to copper becoming the industry standard for interconnects.
Now, too, copper interconnects are starting to hit a bottleneck. Copper interconnects always require a barrier lining material to form a proper wiring structure. As the device shrinks, there is less space available for copper wiring and gasket materials.
The industry is currently looking for other metals that can replace copper interconnects.
Comparison of the performance of carbon nanotubes (CNTs), single-layer graphene (SLG) and few-layer graphene (FLG) with other related interconnect materials (tungsten (W), copper (Cu) and ruthenium (Ru)**IMEC
IBM: Ruthenium is used
The way IBM is looking is to use ruthenium. Ruthenium can scale up to 1 nanometer and above and remains an effective conductor, so no liner is required, which helps save space. Ruthenium formed by the subtractive patterning method also has the potential to be used in a new type of interconnect integration scheme called top through-hole integration. In this case, the interconnect vias are formed at the top of the wire, not below the wire, allowing for the formation of continuous wires and self-aligning vias for the most critical interconnect layers. In addition, the embedded air gap is firmly formed through this top-through-hole integration, which reduces the parasitic capacitance of the interconnect, which will also help to achieve faster, lower power chips. IBM researchers used extreme ultraviolet lithography (EUV) dual-patterning to create test structures on existing machines, and the results showed that a breakthrough could be achieved.
imec, TSMC: use graphene
Unlike IBM's approach, TSMC experimented with using graphene for multi-layer wiring.
The interest in graphene interconnect applications is not surprising. Graphene exhibits high intrinsic carrier mobility (up to 200,000 cm2 v-1 s-1) and large current-carrying capacity (up to 108a cm2). In addition, graphene has high thermal conductivity and competitive robustness against electromigration. It can also be made to atomic-scale thicknesses, which helps mitigate the effect of thickness on RC latency.
TSMC said that when prototyping interconnects of different widths and comparing their resistance to copper interconnects, it was found that graphene interconnects with widths of 15nm or less had lower resistivity than copper interconnects. Graphene's contact resistivity is also four orders of magnitude lower than copper's. Embedding metal ions in graphene can improve the electrical properties of interconnects, making them promising materials for next-generation interconnects.
imec believes that the hybrid structure of graphene and metal is very promising as a candidate for 1nm. In addition, IMEC is also considering ruthenium (RU) as an alternative to copper interconnects.
Change the device architecture
As mentioned above, IBM's efforts for 1nm are not only ruthenium interconnects, but also VTFET architectures. IBM believes that with VTFETs, transistor components are stacked vertically on top of each other, rather than horizontally, which has been the standard for designing chips since the dawn of the computer age. This dramatically increases the number of transistors that can be installed on a single chip, just as the population density of skyscraper cities is much higher than that of townhouse suburbs. IBM's research shows that the scale of VTFET designs can far exceed the performance of the state-of-the-art 2nm node nanosheet design, first introduced by IBM Research in 2021.
IMEC believes that the device architecture that can surpass 2nm is the forksheet architecture. The new forksheet device architecture is a natural evolution of GAA nanosheet devices, allowing the orbital height to be extended from 5T to 43t while still providing performance gains. Alternatively, with the fork plate design, the available space can be used to increase the plate width, further enhancing the drive current.
The four structures on the side of the figure are all CVET variants **IMEC
Intel, on the other hand, believes that it can use the latest form of GAA FET, the stacked CFET field-effect cell architecture. The integration density of this architecture is further enhanced, and N-type and P-type MOS components can be stacked together to allow 8 nanosheets to be stacked, which is twice as many as RibbonFETs. Currently, Intel is working on two types of CFETS: monolithic and sequential. However, Intel's CFET architecture is not a stand-alone proposal, but is the result of a long-term cooperation with IMEC.
Summary
In the world of technology, 1nm is undoubtedly a very attractive existence. However, as we mentioned in the article, 1nm technology, while it has great potential, also comes with a number of challenges.
For many companies and research institutes, 1nm may represent the "holy grail" of technology. It's not just a physical limit, it's a huge business opportunity. For example, 1nm transistors will lead to faster processors, smaller memory cells, more efficient energy storage, and more.
The road to 1nm can be described as complex and twists and turns. From the perspective of industry, these academic breakthroughs may not be used quickly for commercial chip production. After all, the yield of 3nm chips still seems to be a problem. From 3nm to 1nm, how Moore's Law continues, we look forward to more in-depth exploration to overcome the huge challenges faced by 1nm technology.