Despite the increasing complexity of SoCs, multi-core versatility, low power consumption and high performance are still the bellwether of design. For memory interfaces, higher density and lower power consumption are important criteria for evaluating memory solutions, and the new generation of memory interfaces such as DDR5, LPDDR5, GDDR6 and HBM2E are gradually becoming mainstream in the market. Even in the face of DRAM market cycle fluctuations, as well as the pressure of inventory backlog and cost reduction of major storage manufacturers, the new power technology of memory DRAM is still hot, and there is even a momentum to increase investment. Coupled with the driving role of generative AI applications and high-computing power chips, higher bandwidth DRAM interfaces continue to grow strongly.
The advent of the era of AI large models has accelerated the popularization of DDR5 technology
The Jedec (Solid State Technology Association) describes DDR5 as a "revolutionary" memory architecture that caters to the storage and data transfer needs of new technologies such as AI, cloud computing, and the Internet of Things. Compared to DDR4, DDR5 offers higher transfer rates and higher bandwidth, further expanding memory capacity. At the same time, DDR5 also provides the foundation for complex SoC and high-performance computing by adopting lower voltage and advanced transmission efficiency.
DDR5 solves the speed problem first and foremost, with a transfer speed of 6400Mbps doubling the speed of a single DQ (the highest rate in the industry has reached 8400Mbps at the moment). Correspondingly, increased speed also leads to higher density. DDR5 memory supports higher memory density, which means more memory can fit in the same physical space, which is beneficial for users who need to work with large data sets or run memory-intensive applications. Compared with DDR4, DDR5 has a 4x higher capacity to 64GB. The burst length per channel has been increased from 8 to 16, which means that DDR5 will be able to perform two 64-byte operations in the same amount of time compared to DDR4. DDR5 has a 16N prefetch architecture, which gives it a higher speed. In addition, DDR5 introduces more types of training and the addition of multiple TAP DFEs to solve the ISI problem on the transmission link.
On the DIMM side, power management circuitry is provided in the DDR, and the addition of PMIC greatly improves power integrity. Under these conditions, the voltage can be reduced to 11V, lower than DDR4. The distribution of PMIC can reduce problems such as noise and crosstalk, and also provide some help to improve signal integrity.
Reducing power consumption is especially important for device energy savings and extended battery life. DDR5 adds dual-channel support, with two 40-bit channels to improve memory access performance and speed improvement. In terms of details, DDR5 will introduce more temperature sensors in DIMMs, upgrade the sideband signal to I3C, and reduce the design difficulty caused by the increase in rate capacity under multiple upgrades.
Based on the advantages of DDR5 in terms of transmission rate, bandwidth, and capacity, various industries and applications are accelerating towards the new era of DDR5, whether it is PCs, laptops, or artificial intelligence. The generative AI market is booming, and AI servers for large model applications will also drive demand for DDR5.
LPDDR5 technology: higher bandwidth, higher speed, lower power consumption
In February 2019, Jedec released the LPDDR5 standard, which is a leap forward in terms of speed, power consumption, and performance compared to the previous generation LPDDR4X. LPDDR5 uses a clock frequency of 3200MHz and reaches 6400Mbps in terms of data rate, which is 15 times, while LPDDR5X and LPDDR5T can even reach 8500Mbps and 9600Mbps respectively. Although LPDDR5 uses a single 16-bit channel, the storage capacity of the channel itself has been doubled, and it can support multi-bank group mode to further improve data bandwidth.
In terms of power consumption, since the voltage has been reduced to 05V, and with new energy-saving features such as DVFS, Deep Sleep Mode, DQ Replication, and Write X, LPDDR5 successfully reduces power consumption by 45% through the use of dynamic voltage regulation DVFS for further savings. In this case, the memory and controller can reduce the frequency and voltage of the DRAM during channel standby. LPDDR5 supports two core and IO voltages via DVS, with 1. for high-frequency applications05v and 05V operating voltage, 09v and 03V voltage. In addition, by adopting an advanced scalable CA CK clock structure, the timing signoff pressure on the SOC designer can be relieved. The addition of the Write X feature allows a specific all-zero mode to be converted into a contiguous memory location without the need to switch DQ on the channel, further reducing power consumption.
Figure 1 Comparison of LPDDR5 speeds.
Figure 2 Comparison of DDR5 and LPDDR5 technologies.
In terms of the application of LPDDR5, the smartphone market is the first to be hot, and the synchronization is also accompanied by the rise of tablet applications. At present, in terms of automotive intelligence and AI, more and more LPDDR5 technologies will be adopted. On November 28, Changxin Storage officially launched LPDDR5 series products, including 12GB LPDDR5 particles, 12GB LPDDR5 chips in POP packaging and 6GB LPDDR5 chips in DSC packaging. Domestic LPDDR5 particles will usher in a new wave of mid-to-high-end mobile device market.
GDDR6 HBM technology, a professional choice for specialized applications
With the rapid development of display technology, higher frame rates and wider format games also urgently need higher bandwidth and more frequent interactions. As a result, another branch of DDDR, GDDR, has emerged, which is suitable for computing fields with high bandwidth requirements, such as graphics-related computing, data centers, and AI.
At first, the first generation of GDDR was not very different from DDR, but under the influence of market and cost, the two functions gradually parted ways. Since then, the insanely increasing demand for bandwidth has forced GDDR technology to evolve, and the 256-bit GDDR6 bandwidth has reached 768 GBS. The video memory can be directly mounted on the graphics card, which weakens the impact of wiring and signal transmission delay. Therefore, GDDR also has a different technical route from DDR LPDDR: on the one hand, high Prefetch is used, so that 64 bytes (512 bits) of data can be obtained in each cycle (per channel); On the other hand, with the increased burst length method, the GDDR6 burst length is 16 bytes (as with DDR5), which allows the memory to fetch up to 64B cache lines per transfer. GDDR6 can acquire the same amount of data as GDDR5X in two separate channels, while also increasing the density to 16GB.
Figure 3 Comparison of LPDDR5, DDR5, GDDR6 HBM technologies.
As applications become more complex and processors and storage are exchanged more frequently, a technology that provides high bandwidth and high bandwidth is urgently needed to solve the problems of energy consumption and congestion. Compared to GDDR5, HBMs are like highways, with higher bandwidth and much smaller size. HBM is a representative product that has evolved from traditional 2D to three-dimensional 3D, opening the way to DRAM 3D. HBM uses a low-speed clock and compensates for the loss of bandwidth with a large number of buses, enabling widths of up to 4096 bits. Compared with the above-mentioned DDR technology, HBM has the characteristics of higher bandwidth, higher bit width, lower power consumption, and smaller form factor. In HBM2E, the clock and strobe operate at the same frequency, up to 18 GHz for the lowest latency solution. The HBM3 changes the clock architecture by decoupling the traditional clock signal from the host to the device and data select signal, with a maximum rate of 3 for WDQS and RDQS2 GHz for up to 64 Gbps data transfer rate.
Figure 4: Comparison of bandwidth capacity of advanced DDR technologies.
As an important part of SoC chips, DDR is mainly responsible for data exchange between hardware such as hard disks, motherboards, and graphics cards and processors. At present, the pursuit of DDR memory technology with faster speed, higher bandwidth, larger capacity and lower power consumption has become an irreversible development trend, and the design difficulty of DDR modules has increased.
According to the research institute ipnest, the global semiconductor IP market size will reach 66 in 2022$700 million, up 202%。iNest expects the semiconductor IP market size to exceed $10 billion by 2025, growing at a CAGR of 16 from 2021 to 20267%。At present, the growth rate of China's semiconductor IP market is basically the same as that of the global semiconductor IP market, and the market potential is huge.
As new technological trends such as AI, automotive intelligence, and chiplet bring new variables to the IP industry, interface IP, as the most potential subcategory of semiconductor IP, has given domestic manufacturers more opportunities.
Niuxin Semiconductor's DDR4 LPDDR4 multi-customer mass production chasing orders, IP mature and stable
Niuxin Semiconductor is committed to the development and licensing of semiconductor interface IP, and provides related overall solutions based on the best technology. Niuxin Semiconductor cooperates with a number of foundry factories to deploy mid-to-high-end interface IPs such as Serdes and DDR in mainstream advanced and mature processesRelying on the accumulation of technology in subdivided fields, the IP products and related services independently developed by Niu Xin Semiconductor have been used by more than 100 customers.
In terms of DDR IP layout, Niuxin Semiconductor can provide mature and stable DDR3 3L 4 and LPDDR2 3 4 4X MC+DDR complete solutions, DDR4 rate supports 3200Mbps, LPDDR4 4X supports 4266Mbps. In addition to the successful verification test results in the mainstream advanced process nodes at home and abroad 12, 22 and 28nm, it also achieves stable mass production of chips for many domestic customers.
In a case study with a customer, Niu Xin Semiconductor's DDR3 4 LPDDR4 Combo IP makes full use of the advantages of the 12nm platform, with industry-leading power consumption, obvious access efficiency advantages, and supports wire-bonding packages and PCB designs with lower layer counts. moreIt is worth mentioning that DDR IP can still work stably under HTOL, temperature cycle, power supply deviation and other conditions, showing a high degree of reliability. According to the technical support engineer of Niuxin Semiconductor, Niuxin Semiconductor's DDR products use reliable and stable training algorithms, which can improve the instability caused by different DDR topologies and environments. Among them, the design of high-speed DDR Io also benefits from the long-term accumulation of Niuxin Semiconductor in the high-speed interface of Serdes, and some modules used in the Serdes interface provide a reference for DDR design, and the two are complementary to each other.
Niuxin Semiconductor's DDR5 LPDDR5 maintains its advantages, and multi-process platforms are blooming
At present, Niuxin Semiconductor has deployed DDR5 LPDDR5 products under multiple process nodes, covering advanced processes and domestic processes, and the unique design based on digital architecture makes DDR PHY easier to migrate between different processes, and has reached the industry's first-class level in terms of performance balance of bandwidth and latency, as well as area and low power consumption. At the same time, more attention is paid to the support of domestic DRAM particles in development, and special debugging and optimization are carried out to increase robustness, so that customers have a more comprehensive choice in particles.
In order to get the most out of DDR5 LPDDR5, signal integrity analysis must be performed at critical points in the system, such as chips, packages, and PCBs, taking into account the impact of power supply. Niuxin Semiconductor tailors signal integrity and power integrity solutions for customers, around DDR5 LPDDR5, provides a rapid check for signal attenuation and power supply impact on signal, based on rich modeling experience in power and signal networks and high-speed IO, can perform multiple signal networks and power network timing**.
Figure 5: Signal integrity influencing factors.
With the characteristics of high performance and low power consumption, the technical indicators of a variety of IP products of Niuxin Semiconductor are leading in the industry, and are widely used in consumer electronics, network communication, data storage, high-performance computing, Internet of Things, artificial intelligence, automotive electronics, industrial control, medical electronics and other fields. In the future, in the face of the broad market, Niuxin Semiconductor will strive to grasp the opportunities of the times with its years of accumulated experience in chip design and mass production, continue to focus on IP localization and industrial application needs, and continuously inject "core" vitality into the IC design industry through the research and development and innovation of independent intellectual property rights of interface IP.