At the 2024 SEMI International Strategy Symposium, I (referring to Scotten Jones, the author of this article) examines where logic will be headed in a decade's time, from a technical and economic perspective. The following is a discussion of my presentation.
In order to understand the logic, I believe it is useful to understand what makes up a leading-edge logic device. TechInsights provides detailed package analysis reports, which I acquired for 10 7nm and 5nm devices, including Intel and AMD microprocessors, Apple A-series and M-series processors, NVIDIA GPUs, and other devices.
Figure 1 illustrates the composition of the die area.
Figure 1Logic layouts
As you can see in Figure 1, the logic part occupies slightly less than half of the die area, the memory part is slightly less than one-third of the chip area, and the IO, analog, and other parts account for the balance. What I find interesting is that the actual measured SRAM memory area is much smaller than the percentage of system-on-chip (SoC) products that I usually hear people talk about. The graph in the lower right corner shows that there is an outlier, but other than that, the values are tightly clustered.
A single logic takes up almost half of the chip area, so it makes sense to start with the logic part of the design. The logical design was done using a standard cell, and Figure 2 is a floor plan of the standard cell.
Figure 2: Standard unit.
The height of a standard cell is usually expressed as a metal 2 pitch (m2p) multiplied by the number of tracks, but as can be seen from the right side of the figure, the cross-sectional diagram of the device structure must also match the height of the cell and be physically limited by the device. The same goes for the cell width that depends on the contact poly pitch (cpp), and a cross-sectional view of the device structure can be seen from the bottom of the graph, which is again physically constrained.
Figure 3 shows the results of an analysis that determines the actual limits of cell width and cell height scaling. I have a presentation detailing the zoom limits in which there are dozens of slides between Figures 2 and 3, but due to time constraints, I can only present the conclusions.
Figure 3: Logical unit miniature.
Cell width scaling depends on CPP, and the left side of the diagram illustrates how CPP consists of gate length (LG:gate length), contact width (WC), and two contact to gate spacer thicknesses (TSP). LG is limited by leakage, and the minimum LG that can be leaked depends on the device type: planar devices with a single gate are capable of using a channel surface with unrestricted thickness (about 30nm or so); FinFETs and Horizontal Nanosheets (HNS) limit the channel thickness (5 nm) and have 3 and 4 gates, respectively.
Finally, the 2D material introduces a non-silicon material with a channel thickness of <1 nm and can produce LG as low as about 5 nm. Due to parasitic effects, both WC and TSP have limited ability to scale. On top of that, 2D devices may produce about 30nm CPP, compared to today's CPP of about 50nm.
Cell height scaling is shown on the right. HNS provides a single nanosheet stack to replace multiple fins. Then, the development towards stacked devices with CFETS eliminated horizontal NP spacing and stacked NFET and PFET. The current cell height is 150nm to 200nm and can be reduced to about 50nm.
The combination of CPP and cell height scaling can produce a transistor density of about 1.5 billion transistors per square millimeter (1500 mtx mm), compared to today's < 300 mtx mm. It should be noted that 2D materials may be a technology in mid-to-late 2030, so 1,500 MTX mm is not in the timeframe discussed here.
Figure 4 summarizes the processes announced by Intel, Samsung, and TSMC.
Figure 4: Published process nodes.
For each company and year, the device type, whether the back power supply is used, density, power, and performance (if any) are displayed. Power consumption and performance are relative metrics, and Intel does not provide power consumption.
In Figure 4, leading performance and technological innovations are highlighted in bold. Samsung is the first company to go into production of HNS in 2023, Intel won't launch HNS until 2024, and TSMC won't launch it until 2025. Intel is the first company to put the backside power supply into production in 2024, and Samsung and TSMC won't launch it until 2026.
My analysis concludes that Intel is the performance leader with the i3 and has maintained that position during the period shown, with TSMC having a power lead (Intel data is not available) and density leadership.
Figure 5 illustrates our logical roadmap and includes the projected SRAM cell size (more on that later).
Figure 5: Logical roadmap.
From Figure 5, we expect CFETS to be introduced around 2029, increasing logic density and reducing SRAM cell size by nearly half (SRAM cell size reduction has effectively stopped at the cutting edge). We expect the logic density to reach 757mtx mm by 2034.
The logic transistor density and SRAM transistor density are shown in Figure 6.
Figure 6Transistor density**.
Both the logic and SRAM transistor densities are scaling slower, but the transistor density of SRAM has slowed down to a greater extent, and the logic now has a similar transistor density to SRAM.
Figure 7 summarizes the simulated scaling data for TSMC compared to logical and SRAM. Both mock and IO scaling are slower than logical scaling.
Figure 7: Simulation and io-scaling.
For slower SRAM, as well as analog and IO scaling, a possible solution is chiplets. Chiplets enable a cheaper and more optimized process to manufacture SRAM and IO.
Figure 8: Chiplets
The graph on the right side of Figure 8 is from 2021**, which I co-authored with Synopsys. We conclude that even taking into account the increased packaging assembly costs, breaking down a large SoC into chiplets can cut the cost in half.
Figure 9 shows the cost of standardized wafers and transistors for logic, SRAM, and IO (note that the graph has been updated based on the original demo).
Figure 9: Cost**.
The graph on the right shows the cost of a standardized wafer. The cost of logic wafers is targeted at the all-metal stack with an increasing number of metal layers. SRAM wafers have the same nodes, but are limited to 4 metal layers due to the more regular layout of SRAM. io Wafer cost is based on 16nm-11 metal process. I chose 16nm to get the lowest cost FinFET node to ensure adequate IO performance.
The figure on the right is the conversion of wafer cost to transistor cost. Interestingly, IO transistors are so large that they cost the highest even on low-cost 16nm wafers (IO transistor size is based on TechInsights' measurements of actual IO transistors). The cost of logic transistors rises at 2nm, the first TSMC HNS chip node, which is not scaled by much. We expect the second-generation HNS node to scale larger at 14A (which is similar to what TSMC did with its first FinFET node). Similarly, the cost of the first CFET node adds to the transistor cost of one node. In addition to the shrinkage of one-time CFETS, the cost of SRAM transistors is on the rise due to limited shrinkage. The bottom line of this analysis is that while chiplets can provide a one-time benefit, the transistor cost reduction will be modest.
The chart below is our conclusion.