simultaneous multi-threading (s.m.t.Or Intel's preferred hyper-threading is a technology that has been around for more than 20 years. Intel was the first to apply the technology to the Xeon series in 2002, followed by the desktop version of the Pentium series. It was the era of Windows XP, and Intel has been iteratively refining the technology ever since.
For those unfamiliar with the technology, a quick introduction is that HTT allows a physical core to execute multiple instructions in a pipeline stage. This is a low-cost parallelization technique that actually makes the single physical core supported think of as two logical cores for the software. Of course, the actual performance improvement is not directly multiplied by the performance. This is because some resources still need to be shared (cache, integer arithmetic units, floating-point arithmetic units, etc.).
AMD has introduced a slightly different CMT (Clustered Multi-Threading) technology on the Bulldozer architecture, but the performance is disastrous. So when it came to the ZEN (Ryzen) architecture, I just copied Intel's homework and used it to implement similar technologies.
Whether or not Intel is satisfied, the company appears poised to deprecate the technology on next-generation desktop and mobile platforms.
The latest news cites a screenshot of Task Manager from an early A1 version of Intel's 16th Gen mobile platform, Lunar Lake, as rumored to be a screenshot. One of the most interesting is that the number of physical and logical cores shown is 8. This shows that the chip is not activated HTT technology at least.
Of course, Lunar Lake isn't the only series where Intel is rumored to be deprecating HTT technology. Another rumored Intel document also shows that the desktop version of the Arrow Lake-S processor also lacks HTT-related descriptions.
**Fans Incentive Program Intel's cores (energy efficiency cores) no longer support HTT, and combined with the above two rumors, it seems that Intel is also planning to deprecate HTT on traditional cores (performance cores).