1.pci-e
Introduction to the PCI-E bus
PCI-E (PCI-Express) is a general bus specification, which is advocated and promoted by Intel, and its ultimate design is to replace the bus transmission interface inside the existing computer system, which not only includes the display interface, but also includes CPU, PCI, HDD, Network and other application interfaces.
PCI-E uses multiple pairs of high-speed differential signals to transmit data, and the data rate can be 25gbps.5Gbps for Gen 2 or 8Gbps for Gen 3. Depending on the bus throughput bandwidth, you can select x1 x2 x4 x8 x16 x32 mode. x1 x2 x4 x8 x16 x32 refers to the number of lanes on the bus, for example, in x4 mode, 4 pairs of high-speed differential lines are used for each transmitting and receiving, and 16 pairs of high-speed differential lines are used for each transmitting and receiving in x16 mode. Since the number of system lanes can be selected according to the transmission bandwidth needs, PCI-E is very flexible to use. The PCI-E bus protocol adopts a hierarchical structure similar to TCP IP over Ethernet, which is divided into physical layer, data linklayer, and transaction layer from bottom to top. The software interface above the transport layer is compatible with the traditional PCI PCI-X, so the programs developed on the PCI PCI-X interface in the early days can be ported to the PCI-E interface without too many modifications, which greatly saves the cost of upgrading. 
Application scenarios
Due to the high throughput rate, low implementation cost, and mature technology of PCI-E bus, it has become a standard peripheral interface in desktop, notebook, server and other applications, and is becoming more and more popular in many embedded applications that require high-speed data exchange.
1.South Bridge and North Bridge North Bridge (mostly integrated inside the CPU): Hang high-speed devices, such as graphics cards, and memory South Bridge: Hang low-speed devices, such as LPC interfaces, network card 2Peripherals 1) Peripherals with PCI-E interface 2) Other processor systems such as:
1.X1 X2 is used to expand low-speed devices such as network cards, sound cards, and replace PCI slots.
2.X4 to expand medium-speed devices such as RAID cards to replace PCI-X slots.
3.x8 x16 for expanding high-speed devices such as graphics cards and eliminating agp slots.
PCI-E interface definitionIn a data path (lane) of the physical link of the PCI-E bus, it consists of two sets of differential signals with a total of four signal lines. wherein the TX component of the transmitter and the RX component of the receiver are connected using a set of differential signals, and the link is also called the transmit link of the transmitter and is also the receiving link of the receiver; The RX part of the transmitter is connected to the TX part of the receiver using another set of differential signals, and this link is also known as the receive link of the sender, which is also the transmit link of the receiver.
A PCI-E link can consist of multiple lanes, and currently a PCI-E link can support 32 lanes, i.e. 1, 2, 4, 8, 12, 16, and 32 width PCI-E links.
In addition to the TX RX data pair, the PCI-E interface also defines a number of auxiliary signal lines, including PERST signals, RefClk+ and RefClk- signals, WAKE signals, SMCLK and SMDAT signals, PRSNT1 and PRSNT2 signals, JTAG signals, etc. 2.sataAbout SATAIn desktop, notebook, and server applications, hard disks are essential storage media, and the traditional connection interface between hard disks and computer motherboards is a parallel ATA interface. In order to provide higher transfer speeds and more convenient connections, SerialATA (SATA) has replaced parallel ATA as the mainstream of hard disk interfaces. SATA replaces the traditional parallel ATA's 40pin cable with a 7-pin connector, making it easier to connect and have higher transmission rates. SATA uses two pairs of differential lines to provide bidirectional data transmission and reception, so it can provide higher transmission rates with a relatively small signal swing, and the differential lines themselves have better anti-interference capabilities and smaller EMI, so they can support higher signal transmission rates. The SATA bus uses embedded clock frequency signals, which has more error correction capabilities than ever before, and can check transmitted instructions (not only data) and automatically correct errors if they are found, improving the reliability of data transmission. The most obvious difference between SATA and the previous one is that it uses thinner cables, which is conducive to air circulation inside the chassis and increases the stability of the entire platform. ◆Application scenariosIt is mainly used for data transfer between the motherboard and a large number of storage devices such as hard disks and optical drives.
Interface definitionThe signal part of the SATA interface consists of 7 cables, of which 3 ground wires can weaken and eliminate interference between serial cables, and the other 4 signal wires are differential in pairs, which serve as transmit and receive respectively. 
3.ethernetIntroduction to Ethernet technology
Ethernet is widely used in areas such as PCs and data communications. The technology of Ethernet, which is now widely used, has developed very rapidly since the introduction of the 10BASE-T standard in the 90s of the 20th century. At present, 10M, 100M, and 1000M Ethernet based on twisted pair media are commonly used, and 10G and higher rate Ethernet technology is also widely used in servers, data exchange and other fields. 10BASE-T, 100BASE-TX, and 1000BASE-T are all Ethernet standards that use twisted pair media and RJ-45 connectors (sometimes called crystal heads) for data transmission. 
Application scenarios
Ethernet. Interface definition (take RJ45 as an example).
There are 8 pins on the RJ45 connector, which can connect 4 pairs of twisted pairs. Among them, 10base-t and 100base-tx only use two pairs, one pair is used to transmit and the other pair is used to receive. In the 1000BASE-T standard, four pairs of twisted pairs will be used at the same time, and each pair of twisted pair will transmit and receive data at the same time. 
4.mipiAbout MIPI
MIPI (Mobile Industry Processor Interface) is an alliance established in 2003 by ARM, NOKIA, ST, TI and other companies, with the purpose of standardizing the interfaces inside the mobile phone, such as camera, display interface, RF baseband interface, etc., so as to reduce the complexity of mobile phone design and increase design flexibility. There are different workgroups under the MIPI Alliance, which define a series of internal interface standards for mobile phones, such as camera interface CSI, display interface DSI, RF interface DIGRF, microphone speaker interface Slimbus, etc. The benefit of the unified interface standard is that mobile phone manufacturers can flexibly choose different chips and modules from the market according to their needs, making it faster and easier to change the design and functionality. At present, the mature MIPI applications include the CSI interface of the camera, the DSI interface of the display, and the DigiRF interface between the baseband and the radio. UFS, LLI and other specifications are in the process of being gradually formulated and improved. 
Application scenariosInternal interface for mobile communications. 
Interface Definition (MIPI DSI).
The physical layer (PHYer) of CSI DSI is developed by a dedicated workgroup, and the current PHY standard is D-PHY. The D-PHY uses 1 pair of source-synchronized differential clocks and 1 4 pairs of differential data lines for data transmission. The data transmission adopts the DDR method, that is, there is data transmission on the upper and lower edges of the clock. MIPI-DSI interface
5.usbIntroduction to USB Bus
USB is an external bus standard that regulates the connection and communication between computers and external devices. The USB port is hot-swappable. The USB port allows you to connect a variety of peripherals, such as a mouse and keyboard. USB was launched in 1996 by Intel and other companies at the end of 1994, and has successfully replaced serial ports and parallel ports, and has become a necessary interface for today's computers and a large number of smart devices. USB system device types include host, hub, and device. The USB host is responsible for managing the IO system and application software, managing peripheral enumeration, and initializing operations on specific peripherals during operation. The USB hub provides an expanded USB peripheral interface that can cascade up to 5 levels and connect up to 127 USB devices. The USB device accepts operations initiated by the host and sends or receives data. 
USB its bus standard mainly experienced: USB11 - Support 1. for low speed (halfspeed).5Mbps and 12Mbps at Fullspeed; usb2.0 - 480Mbps for high speed; usb3.0 - supports 5Gbps at superspeed.
Application scenariosUSB has the advantages of fast transmission speed, easy to use, hot-swappable, flexible connection, independent power supply, etc., and can connect a variety of peripherals such as keyboards, mice, and mass storage devices, and the interface is also widely used in smartphones. The interaction between computers and other smart devices and external data is mainly based on network and USB interfaces.
Interface definition
usb 3.0 in the original USB 20 on the basis of the 4 wires (VCC, GND, D, D) 2 pairs of differential wires are added, so that USB 3There are a total of 8 wires on the 0 interface. The original 4 roots are fully compatible with the original USB 20 devices; The two additional pairs of differential lines adopt full-duplex mode, with one pair of lines responsible for transmitting and the other pair of lines responsible for receiving, and both transmit and receive can achieve a data rate of 5Gbps.
6.hdmiIntroduction to HDMI
The High Definition Interface (HDMI) is a fully digital and sound sending interface that can send uncompressed audio and signals. HDMI can be used in set-top boxes, PCs, PCs, TVs, game consoles, amplifiers, digital audio and televisions and other equipment. HDMI can send audio and signal at the same time, because the audio and signal use the same cable, greatly simplifying the installation difficulty of the system line.
According to the definition of the HDMI standard, HDMI devices are divided into source devices, sink devices (receiving devices), and cable devices. Source equipment is to produce HDMI signal output, such as set-top boxes, digital cameras, computers, game consoles, etc.; A sink device receives and displays an HDMI signal, such as a TV, projection, monitor, etc. In addition to this, there is also a repeater device (relay device) that is used to receive HDMI signals and redistribute outputs, so that the repeater device has both an interface for a sink device and an interface for a source device.
Application scenariosHDMI can transmit audio and video signals at the same time, and can be used in set-top boxes, ** machines, personal computers, TV amusement instruments, amplifiers, digital audio and televisions.
Interface definitionOn the HDMI bus, the main signal transmission is 4 pairs of differential signals, including 1 pair of differential clock signals and 3 pairs of differential data signals. Normally, the clock frequency on the clock line is 1 10 of the data transmission rate on the data line, for example, the data rate on each pair of data lines is 1At 485Gbps, the clock signal frequency transmitted on the clock line is 1485mhz。In addition to the ***S signal, there is also a Hot Plug (HPD signal hot swap control) on the HDMI bus for device insertion detection, a DDC channel (Display DataChannel) for receiving the device's EDID information reading, and a 5V signal for powering peripherals.
displayportdisplayportIntroduction
DisplayPort (DP) is a digital interface standard developed by a consortium of PC and chip manufacturers and standardized by the Electronic Standards Association (VESA). The interface is free of authentication and license fees, and is mainly used for the connection between the source and the display and other devices, and also supports the carrying of audio, USB and other forms of data. This interface is designed to replace traditional VGA, DVI, and FPD-Link (LVDS) interfaces. With active or passive adapters, the interface is backward compatible with legacy interfaces such as HDMI and DVI. DisplayPort can be used to transmit audio and ** simultaneously, each of which can be transmitted separately without the other. The DP interface (DisplayPort) supports not only Full HD display resolution (1920 1080), but also 4K resolution (3840 2160) and the latest 8K resolution (7680 4320). The DP interface not only has a high transmission rate, but also is reliable and stable.
The signal transmitted by the DisplayPort interface consists of the data channel signal of the transmitted image and the auxiliary channel signal of the status and control information related to the transmitted image, including the main link, aux channel and link training of the DisplayPort data transmission.
Main link: A primary link is a one-way, high-bandwidth, low-latency channel that transmits synchronous data streams, such as uncompressed ** and audio. Aux Channel: The aux channel is a half-duplex, bidirectional channel used for link management and device control. Application scenarios
DisplayPort is preferred on computers and monitors, and HDMI is preferred on home entertainment devices; Display color calibration: DisplayPort is preferred, because the RGB range of the HDMI interface will be missing; Multi-screen expansion: DisplayPort supports multi-screen expansion, while HDMI only supports a single screen. Interface definition
8.lvdsIntroduction to LVDS
LVDS, or Low Voltage Differential Signaling, is a low-voltage differential signaling technology interface. It is a digital signal transmission mode developed to overcome the shortcomings of high power consumption and EMI electromagnetic interference when transmitting broadband and high bit rate data in TTL level mode. The LVDS output interface uses a very low voltage swing (about 350mV) to transmit data differentially on two PCB traces or a pair of balanced cables, i.e., low-voltage differential signal transmission. The LVDS output interface can be used to make the signal be transmitted at a rate of several hundred Mbits on a differential PCB line or balanced cable, and due to the use of low-voltage and low-current driving mode, it achieves low noise and low power consumption.
LVDS signal transmission consists of three parts: differential signal transmitter, differential signal interconnect, and differential signal receiver.
Transmitter: Converts an unbalanced TTL signal into a balanced LVDS signal. There are separate and integrated ones.
Receiver: Converts the balanced LVDS signal into an unbalanced TTL signal with a high input impedance.
Interconnects: Includes connection wires (cable or PCB traces), termination matching resistors. According to IEEE regulations, the resistance is 100 ohms. We usually choose 100 or 120 euros.
Application scenarios
LVDS is becoming more widely used in systems that require high signal integrity, low jitter, and co-patterning. It is widely used in LCD displays of 17inch and above.
Interface definition
Interface classification: single-channel 6-bit LVDS: single-channel transmission, 6-bit data for each primary color, a total of 18-bit RGB data; Dual-channel 6-bit LVDS: dual-channel transmission, 6-bit data for each primary color, 18-bit odd-path data, 18-bit even data, a total of 36-bit RGB data; Single-channel 8-bit LVDS: Single-channel transmission, 8-bit data for each primary color, a total of 24-bit RGB data; Dual-channel 8-bit LVDS: Dual-channel transmission, each primary color uses 8-bit data, odd-path data is 24-bit, and even channel data is 24-bit, a total of 48-bit RGB data. Single-channel 6-bit LVDS
Single-channel 6-bit data (if it is a 6-bit Y3M P, this set of red lines does not have this set of lines) has 4 sets of differential lines, 3 sets of signal lines, and one set of clock lines. y0m、y0p、y1m、y1p、y2m、y2p、clkout_m、clkout_p。A single channel of 8-bit data has 5 sets of differential lines, 4 sets of signal lines, and one set of clock lines. They are y0m, y0p, y1m, y1p, y2m, y2p, clkout m, clkout p.
— Fengke Zhuochen —
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