1) SNSB5 and SNSB10 sample preparation information is as follows:
Material information involved:
Solder - Solidus Temperature - Complete melting temperature
snsb5- 240-248
snsb10-248-254
Chip: The surface of the Si chip forms a Ti Ni Au layer = 100 100 100nm; SI chip 3x3x048mm
Copper plate: surface 800 polishing paper polishing;
Copper plate: 10 10 12mm；Solder lug: 25×2.5×0.12mm – Flux: Senju Metal Industries Deltalux 529D-1; ——Reflow oven: infrared heating, the reflow temperature is higher than the upper limit of the melting point 30, the vacuum is 5pa, and the chip is pressurized 002n。Clean with alcohol after welding. The study was conducted using differential scanning calorimetry (DSC) at a heating rate of 10 min.
Figure 1: Schematic representation of the test sample2) Sample observation conditionsThe sample was placed in epoxy resin and sliced, and the section of the slice was polished with 500-4000 mesh polishing paper, and then treated with 1um of alumina polishing liquid. After polishing, microscopic tissue observation was performed using a microscope and an electron probe X-ray microanalyzer (EPMA, similar to EDS).
3) Accelerated testing
a- Power cycle test.
Figure 2 shows the temperature profile in the power cycling test (PC test). Test condition: JEIT0-ED-4701-602. The cycle curve is 100 -200, the cycle time is 20 seconds, heating 2s + cooling 18s. Tests were conducted with 1k, 5k, and 10k cycles. After testing, fault cracks were observed using SAT and solder joints were observed using EPMA in cross-section. The thickness of the imc layer at 10 points is measured in the cross-section, at 10 m intervals.
Figure 2: Temperature profile B-burn-in test in power cycling.
Thermal aging tests are carried out using furnaces, which are carried out under isothermal conditions at 100 and 200 °C. 8 and 556 hours, equivalent to 1K, 5K, 10K PC tests. After the test, the cross-section of the weld layer was observed using EPMA. Also in the cross-sectional view, the thickness of the IMC layer is measured at 10 point intervals. 4) Comparison of results
4.1 Microstructure of the weld layer.
Figure 3 shows the optical image as well as the cross-sectional backscattered electron image combined with SNSB5 and its EPMA analysis. Looking at the map, SN and Cu were detected in the IMC formed in the Cu SNSB5 solder layer.
Fig. 3: SNSB5 weld cross-section 4 shows the electronic images of the optical and backscatter images of the SNSB10 weld cross-section and their EPMA analysis results, EPMA spectrum analysis results, and the presence of SB-SN in the SN-Cu layer and in the solder layer with SNSB10 in IMC. Figure 5 shows the sn-sb binary phase diagram, from which it can be seen that the studied snsb alloy consists of the -sn+sb-sn phase. In addition, the distribution of SBSN particles was observed in SNSB10. 
Fig. 4: SNSB10 weld cross-section
Figure 5, SNSB Binary Phase Diagram 42.Power cycling test. Figure 6 shows SAT images of SNSB weld layer PCK, 5K, and 10K solder layers after 10K cycles. In the figure, the SNSB5 solder joint** is now very noticeable at 1K CyCl, and only appears at 5K CyCl in the solder of SNSB10. It can be seen that SNSB10 solder joints are more reliable than SNSB5. Figure 7 shows a backscattered electron image of a solder cross-section after a power cycling test. Although cracks are already present in the solder layer of SNSB5, the crack progresses at the interface between the solder and the chip, and the crack progresses in the solder to form a jagged pattern at the solder layer with SNSB10. In SNSB5, the CTE of the SNSB alloy is quite different from the CTE of SI, so cracks are easy to form, and cracks grow solder and chips at the solder interface. In SNSB10, as the SNSB content increases, the CTE of the SNSB alloy decreases and approaches Si, so cracks are prone to grow at the solder joints. In addition, the coarse SBSN compound in SNSB alloy is effective in preventing crack propagation. (So the reliability of soldering in DBC Heatsink should also be better).
Figure 6, Scanning acoustic tomography image of a solder joint after a power cycling test.
Figure 7, Backscattered electron image of a cross-section of the post-PC solder joint (SNSB5 crack closer to the chip side).
Figure 8, the backscattered electron image of the IMC layer in the solder layer interface after the power cycling test sn-sb cu. In the image, two IMC layers are observed in the SN-SB CU solder layer. According to the quantitative analysis results, the dark gray layer and the bright gray layer are inferred to be Cu3Sn and Cu6SN5, respectively, and these IMC layers will thicken with the increase of power cycles. 
Figure 9 shows the IMC layer thickness versus the processing time for the PC test, and the IMC layer thickness of the weld layer for the two alloys varies with increasing processing time. Compared to SNSB5, SNSB10, the differential layer of IMC growth kinetics is negligible.
4.3.Thermal aging test.
Fig. 10 and Fig. 11 show electron images of the backscatter cross-section of the SN-SB solder joint after the thermal aging test at 100 and 200, respectively. In the diagram, the IMC layer can be seen in the two SN-SB CU solder layers, independent of the aging temperature. The dark gray and light gray layers are inferred to be CU3SN and CU6SN5, respectively, and the imc is also visible on the solder layer after the PC test. Figures 12 and 13 show the relationship between the 100 and 200 imc layer thickness and the square root of the thermal aging time, respectively. The thickness of the imc layer increases with the increase of thermal aging time and aging time, and the relationship between the thickness of the imc layer and the square root of the thermal aging time at constant temperature is plotted as follows.
x is the thickness of the imc layer, k is the mutual diffusion coefficient, t is the thermal aging time, and x0 is the thickness of the imc layer in the initial state of welding. Compared to SNSB5 and SNSB10, the difference in the growth kinetics of the IMC layer in the two weld layers is negligible. Comparing with the power cycling test results, such as Figure 9, the IMC layer is thicker than the PC test at 200 and thinner at 100. Figure 14 shows the relationship between the average thickness of the IMC layer in the SN-SB CU solder layer and the actual processing time of the PC test1 5. This time corresponds to the time the weld is exposed to temperatures above 160 °C, and the graph also shows the relationship between the average thickness of the IMC layer in the solder layer and the 200 heat aging time. The thickness of the IMC layer in the graph is obtained by subtracting 100 degrees of aging from each data, as shown in Figure 12. As can be seen from the graph, when the processing time in the PC test is defined as the time the weld layer is exposed to temperatures in excess of 160 °C, the growth kinetics of the IMC layer in the power cycle are in good agreement with the kinetics of 200 years of aging. This means that by studying the growth kinetics of the IMC layer near the peak temperature of the power cycle, the growth kinetics of the IMC layer in the power PC test can be studied.
Figure 10, backscattered electron image of the cross-section of the imc layer formed in the interface of the SN-SB Cu solder layer after aging.
Figure 11, backscattered electron image of the cross-section of the imc layer formed in the weld interface of the sn-sb cu weld layer.
Figure 12, square root plot of IMC layer thickness versus aging time at 100.
Figure 13, square root plot of IMC layer thickness versus aging time at 200.
Fig. 14 shows the relative thickness of the SN-SB Cu in the imc layer of the solder layer as a function of the actual processing time (1 5) in the PC and the aging time in the 200 burn-in test.
5) Conclusion(1) In PC, the life of the chip solder layer SNSB10 is good SNSB5. Cu3SN and Cu6SN5 are observed in two SN-SB CU solder layers, two Cu-SN imc layers. The thickness of the imc layer in both solder layers increases with the processing time. (2) In the thermal aging test, a similar IMC layer is formed at the weld interface of the two SN-SB Cu weld layers. For the growth kinetics of the IMC layer, the trend is similar to that of the PC test. (3) Comparing the two tests, the aging test of 100 and 200 and the PC test in the temperature range of 100-200, it is found that when the PC operation time is defined as the exposure of the solder layer to a temperature of more than 160, the growth kinetics of the IMC layer of the PC test are more consistent with the aging test of 200, which means that the growth kinetics of the IMC layer in the PC can be studied by studying the growth kinetics of the IMC layer at the temperature near the peak temperature of the PC.