Recently, imec announced very large-scale spin-orbit-transfer MRAM (SOT-MRAM) devices that have achieved record-breaking performance, with switching energies of less than 100 femtojoules per bit and endurance of more than 10 to the power of 15.
These results make SOT-MRAM a promising candidate to replace SRAM as the last level of cache in high-performance computing (HPC) applications. Just like SRAM, it offers high switching speeds (in the sub-nanosecond range) and unlimited durability.
In addition, because they are non-volatile, the SOT-MRAM bit cells achieve lower standby power consumption than SRAM at high cell densities. In addition, the SOT-MRAM bit cell can be made much smaller than the SRAM cell, which translates into higher bit packing density.
IMEC experimentally explores the scaling potential and limitations of single vertical SOT-MRAM devices processed on 300mm wafers, the first-ever study report on the scalability of SOT-MRAM devices. At IEDM 2023, they showed that shrinking the SOT track not only reduces the footprint of the SOT-MRAM unit, but also greatly improves the performance and reliability of the unit.
The SOT track is a layer made of metals such as tungsten (W) or platinum (PT) that sits beneath the magnetic tunnel junction (MTJ), the actual switching element of the SOT-MRAM device. The SOT track is used as an in-plane current injection layer, which is introduced to decouple the read and write paths.
In a traditional SOT-MRAM design, the SOT track occupies a larger area than the actual MTJ column, providing sufficient margin for coverage process control," explains Sebastien Couet, Project Director Magnetics at IMEC. "But this leads to wasted energy because some of the current flows outside the MTJ area. We have extended the SOT-MRAM devices to the limit, and the SOT orbital and MTJ pillars have comparable dimensions (critical size of about 50 nm). For these devices, we observed a switching energy of less than 100 femtojoules (FJ) per bit, i.e., a 63% reduction compared to conventional designs. This helps solve the remaining challenges of SOT-MRAM, which has traditionally required high current for write operations. ”
Scaling the SOT track improves the durability of the memory because it reduces Joule heating within the SOT layer.
With more than 1015 programmed erase cycles, we experimentally validated our hypothesis that the SOT-MRAM unit can have infinite endurance – an important requirement for cache memory," says Couet.
Our data provides valuable input for circuit designers to perform design technology co-optimization (DTCO) for SOT-MRAM technology – a trade-off between performance improvement and design margin – at advanced nodes. Future work will focus on materials engineering to further reduce the switching energy per bit and optimize the bit cell configuration to further reduce the cell area compared to SRAM. In the long term, this experience will also be transferred to the development of voltage-gated (VG) SOT-MRAM multi-column devices – iMEC's ultimate solution for high-density embedded memory applications. Sebastien Couet adds.
We will witness the death of SRAM?
This year, the 68th annual IEEE International Electronic Devices Meeting (IEDM) is back in full swing, with nearly 1,500 engineers from around the world returning to downtown San Francisco each year to discuss the latest developments in the semiconductor industry. While there are plenty of interesting ** in academia and industry, the one from TSMC brings terrible bad news – while the logic is still expanding more or less along the historical trend line, the SRAM expansion seems to have completely collapsed.
At the conference, TSMC talked about the original base N3 (N3B) node as well as the enhanced (N3E), which is a slightly more lenient variant of N3B. TSMC demonstrated that the prototype test chip was equipped with a logic circuit consisting of more than 3.5 billion transistors and a fully operational 256Mbit SRAM macro (Figure 1). The SRAM memory cell has an area of 00199 m 2, the smallest ever. We confirm that the SRAM macro is even at 0It also works perfectly at 5V (Figure 2).
Interestingly, for the new N3E node, the high-density SRAM bit cell size reaches 0021 m, which is exactly the same size as the bit cell size of their n5 node, and is not shrinking. The N3B variant isn't expected to make it into much of the product, but does have scaled SRAM bit cells;However, at 0At 0199 m, it shrank by only 5% (or 0.).95 times).
In terms of rough memory density (assuming ISO auxiliary circuit overhead), N3E is roughly 318 mib mm, and will increase to 3355 mib mm or 175 mib mm (230 kb) improvement.
This is some serious bad news!From this point of view, although both N3B and N3E are said to offer 16x and 17x chip-scale transistor scaling, but 1 for SRAM0x and 105x scaling is catastrophic. Now, we're still hoping that TSMC will roll out a denser SRAM bit cell variant for the N3 at some point, and we do expect to see some sort of scaling of SRAM in the future, but the good old miniature SRAM scaling seems to be dead.
Consider a hypothetical 10 billion transistor chip with 40% SRAM and 60% logic, sitting on TSMC N16. Ignoring practical constraints and simulating physics etc., such a hypothetical chip would be about 255 square millimeters, of which 45 square millimeters or 176% for SRAM. Scaling down the exact same chip to n5 will result in a 56 square millimeter chip with 1258 square millimeters or 22 of the chip5% for SRAM. Scaling the chip further down to N3 (based on our initial but not fully confirmed value) will result in a 44 mm² chip with the same SRAM density of 1258 square millimeters, which now occupies almost 30% of the area.
Of course, this effect will not be felt equally in all aspects. The percentage of on-chip SRAM and cache varies depending on the target market and overall capability. However, for some AI hardware startups, where the architecture requires a significant portion of the chip to be covered by SRAM, these engineers will encounter more challenges sooner than others.
The collapse of SRAM scaling is not limited to TSMC. We've been pointing out the issue of sRAM scaling slows down for a while now. For example, while Intel is still scaling down its SRAM bit cells, the company's recently announced Intel 4 process SRAM scaling has gone from a historical 05-0.6x slowed down to 07-0.8 times. For Intel 4, our estimated density (ISO auxiliary circuit overhead compared to TSMC) is 278 mib mm or 4 mib mm or 13% behind. It's not unrealistic to expect Intel's Intel 3 process to match or beat them.
So, where do we go from here?In fact, the only viable alternative to SRAM at the moment is more SRAM, so we expect SRAM to take up more area directly. That's not to say we don't expect more SRAM extensions. While we do expect TSMC and other foundries to produce denser SRAM, the historical expansion seems to have officially come to an end. Some research institutes, such as IMEC, have proposed higher density SRAM bit cells. For example, at last year's IEDM 2021, IMEC demonstrated an SRAM density of about 60 mib mm, roughly double the density of today, at a hypothetical "beyond-2nm node" that uses utilizing forksheet transistors and an advanced double-sided interconnect scheme.
In addition to SRAM, the industry has been working on many other alternative memory architectures. Emerging memory technologies include MRAM, FERAM, NRAM, RRAM, STT-RAM, PCM, and more. Compared to SRAM, these emerging memory bit cells offer unique trade-offs, such as higher density at lower read and write specifications, non-volatile capability, lower read/write cycle capability, or lower power consumption at potentially lower densities or speeds. While they are not a drop-in replacement for SRAM, moving forward they may take on the role of Level 4 or Level 5 caches, where lower performance trade-offs can be offset by higher density.
At the moment, the industry seems to have reached an interesting inflection point.
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