Recently, Synopsys and Intel developed the first test chip using the Universal Chiplet Interconnect Express (UCIE) protocol to connect chiplets manufactured in different processes.
The test chip demonstrates UCIE traffic between the Synopsys UCIe PHY IP and the Intel UCIe PHY IP and simulates each test chip using the Synopsys VCS Functional Verification Tool.
Intel's test chip, Pike Creek, consists of Intel UCIe IP chiplets manufactured based on Intel 3 technology and paired with Synopsys UCIe IP test chips built on TSMC's N3 process. Successful pairing mimics chip mixing and matching that can occur in real-world multi-chip systems, demonstrating that this approach is commercially viable.
The combination of devices built on different process technologies is key to increasing system complexity in a single package using the UCIe protocol.
Manuel Mota, senior product manager for high-speed interface IP at Synopsys Solutions Group, said the collaboration revealed some lessons that they plan to share with the UCIE Alliance.
Since silicon manufacturing takes a long time, and verifying that everything is working as expected can also be costly and time-consuming, finding a way to use existing test chips or silicon can be a good way to evaluate compatibility.
Designing a multi-chip system involves extensive planning, especially when it comes to reusable package or board designs. Building as much flexibility as possible into the board is one way to provide options for future use.
Open standards like UCIE provide confidence in interoperability. When a company controls both ends of the chain, there is no need to worry about whether each party will cooperate. But looking ahead, in the next few years, he expects to see more companies reluctant to build both sides at the same time, instead choosing to buy components from the market that are likely to be manufactured with different technologies. This was highlighted at the recent DVCon Europe chiplet panel meeting.
By allowing design partitions to include multiple process nodes, chiplets help reduce the manufacturing cost of advanced nodes. Mota says that without standards, IP availability is limited, and selecting process nodes based on IP availability is not the best approach. The UCIE Test Chip Interoperability Demo provides solid evidence for mix-and-match IP designs and lays the foundation for an open chiplet ecosystem.
One of the advantages of a multi-chip system architecture is that it can be composed of chips from different vendors for different process nodes. This provides flexibility in terms of cost and optimizing power, performance, and area (PPA). UCIE is a key element in bringing different components together, enabling them to communicate with each other while supporting a range of advanced packaging technologies.
While a UCIE-compliant multi-chip system may work well during development, testing, and manufacturing, the project needed to ensure that the system's chip-to-chip connectivity remained reliable from the start and in the field. This is where UCIe IP comes into play.
UCIe IP typically consists of a controller that is used to achieve low latency between chips based on common protocols such as PCIe, CXS, and streaming protocolsA PHY for high-performance and low-power connectivity in the packageand Verify IP to accelerate verification convergence. Built-in testability capabilities enable you to test defective chips during the bare die testing phase. In addition to these testability features for known good chips, IP can also provide cyclic redundancy check (CRC) or parity for error detection and retry capabilities to correct detected errors.
Intel said it plans to continue working with Synopsys to further develop its UCIe technology, and that close collaboration across the semiconductor ecosystem is critical for chip designers to realize the benefits of these complex, interdependent designs.
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