At the IEDM conference, TSMC charted a course for offering a chip package containing 1 trillion transistors, as Intel revealed last year. These behemoths will come from a collection of 3D-packaged chiplets on a single chip package, but TSMC is also working on developing chips containing 200 billion transistors on a single chip of silicon. To achieve this, the company reaffirmed its commitment to 2nm-scale N2 and N2P production nodes as well as 1The 4nm-scale A14 and 1nm-scale A10 manufacturing processes are expected to be completed by 2030.
In addition, TSMC expects advancements in packaging technology (CODOS, INFO, SOIC, etc.) that will enable it to build large-scale multi-chip solutions with more than a trillion transistors around 2030.
The TSMC slides at the IEDM conference foresaw advances in packaging technology. (*TSMC).
In recent years, the development of cutting-edge process technologies has slowed down due to the technical and financial challenges faced by chipmakers. TSMC faces the same challenges as other companies, but the world's largest foundry is confident that with the launch of TSMC 2nm, 14 nm and 1nm nodes.
NVIDIA's 80 billion transistors GH100 is one of the most complex monolithic processors on the market, and according to TSMC, there will soon be even more complex monolithic chips with more than 100 billion transistors. But building such large processors is becoming increasingly complex and expensive, so many companies opt for multi-chip designs. For example, AMD's Instinct Mi300X and Intel's Ponte Vecchio are made up of dozens of chiplets.
According to TSMC, this trend will continue, and in a few years we will see multi-chip solutions consisting of more than a trillion transistors. But at the same time, monolithic chips will continue to get complex, and according to one of TSMC's presentations at IEDM, we will see monolithic processors with up to 200 billion transistors.
For 1 trillion transistors, Intel is just as confident.
On December 9, Intel demonstrated a key technology for scaling transistors to 1 nanometer and beyond using the rear power contact at IEDM 2023 (2023 IEEE International Electronics Conference). Intel says it will integrate 1 trillion transistors in a single package by 2030.
Powervia backside power technology is expected to be available with the Intel 20A process node in 2024.
Intel said it will continue to advance Moore's Law research, including 3D stacked CMOS transistors with backside power and direct backside contacts, extended paths for backside power R&D breakthroughs such as backside contacts, and large-scale monolithic 3D integration of silicon and gallium nitride (GaN) transistors on the same 300mm wafer instead of a package.
With the continuous advancement of semiconductor technology that follows Moore's Law, the integration of semiconductor chips is getting higher and higher, and the unit of measuring the microscopic integration density of chips has also shifted from nanometers to angsts (1 angstromie is equal to 10 billionths of a meter, which is one-tenth of a nanometer).
We are entering the Angstrom era of process technology, and as we look to the future after the realization of the 'five process nodes in four years' plan, continuous innovation is more important than ever. "Intel has demonstrated continued progress in Moore's Law research, demonstrating our ability to develop leading-edge technologies that enable further scaling of transistors and powering them with high energy efficiency for the next generation of mobile computing." ”
According to the International Data Corporation (IDC), the global AI hardware market (server) will grow from $19.5 billion in 2022 to $34.7 billion in 2026, with a five-year compound growth rate of 173%。Among them, the share of the server market for running generative AI in the overall AI server market will increase from 119% to 31 in 20267%。
According to Intel, the technology, including PowerVIA backside power supply technology, glass substrates for advanced packaging, and Foveros Direct technology, is expected to be in production by 2030.
Mauro Kobrinsky, director of technology development at Intel, said, "Moore's Law is driving more transistor integration, which in turn is driving more layers and smaller wires, increasing complexity and cost. Signal and power wires must be provided at each level, which often leads to optimization compromises and resource contention, creating interconnection bottlenecks that make things increasingly challenging. "Backside power supplies fundamentally change this by using power vias on both sides of the device and in vertical interconnects. We will be able to do it next year in semiconductors Intel 20A (2nm) and 18A (1.).8nm), which means fewer wires up front, so we can loosen the spacing and no longer need to make optimization compromises. ”
In addition to power vias, our research also involves backside contact, which allows us to connect transistors on both sides of a connector for the first time. We've been able to make these contacts in our research, and the front and back contacts don't require the use of power vias for routing. This allows us to reduce the capacitance of the battery, improve performance and reduce power consumption. Kobrinsky said.
Intel believes that transistor scaling and backside power are key to meeting the world's exponentially increasing demand for more powerful computing power. With the advancement of backside power technology and the adoption of new 2D channel materials, Intel is committed to continuing to advance Moore's Law and achieve the integration of 1 trillion transistors in a single package by 2030.
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