On December 28, according to foreign media Tomshardware, TSMC, a major wafer foundry, shared its latest Roadmap at the IEDM conference, planning to launch a 1nm-level A10 process in 2023 to achieve the integration of 20 billion transistors on a single chip, and rely on advanced packaging technology to achieve the goal of integrating 1 trillion transistors on a single package.
Specifically, according to TSMC's plan, the 2nm-class N2 process will be mass-produced in 2025 and the N2P process will be mass-produced around 2026. New technologies such as copper filling will enable the integration of more than 100 billion transistors on a single chip, and more than 5,000 transistors in a single package with the help of advanced 3D packaging technology.
After 2027, TSMC will also mass-produce 1The 4nm-class A14 process will be mass-produced in 2030 for the 1nm-class A10 process, realizing the integration of more than 200 billion transistors on a single chip, and more than 1 trillion transistors in a single package with the help of 3D packaging technology.
Although the advancement of Moore's Law has continued to slow down in recent years, TSMC is convinced that with the development of 2nm, 1With the introduction of 4nm and 1nm processes, semiconductor chips will continue to improve performance, power consumption and transistor density in the next five to six years.
One of the most complex monolithic processors on the market today is Nvidia's GH100, with 80 billion transistors. TSMC said that soon, more complex single-chip chips will appear, and the number of transistors will exceed 100 billion, but the process will become more complex and the cost will become higher, so many companies will choose multi-chip package designs, such as AMD Mi300X and Intel Ponte Vecchio, which are composed of dozens of chips.
Editor: Xinzhixun-Rogue Sword.