The full name of BGA is "Ball Grid Array", or "Ball Grid Array Package". At present, the vast majority of Intel mobile CPUs use this packaging method, such as all Intel processors ending in H, HQ, U, Y, etc. (including but not limited to low voltage). BGA can be an extreme product of LGA and PGA, and they can be replaced at will, once BGA is packaged, unless through professional instruments, it is impossible for ordinary players to disassemble and replace it in a normal way, but because it is done at one time, BGA can be made shorter and smaller in size.
The competitive mobile market forces designers to accomplish a challenging goal: lower cost, but better performance. Chip-package-system (CPS) collaborative analysis is one of the important breakthrough methods. It is designed to enable mobile AP system designers to discover and minimize over-designs that would never be discovered by optimizing each chip, package, and board level. In the context of increasing digital interface speeds, signal integrity (SI) analysis becomes a necessity to ensure IC-package-PCB implementation. In the following, we introduce Ansys' strategy for extracting the S-parameters of differential signals in BGA packages, that is, with the help of ANSYS' HFSS 3D Layout professional 3D SI PI analysis tool, to analyze the SI problems of BGA. The two pairs of differential signals analyzed in this analysis are shown in red net below: (rxdata3+, rxdata3 and rxdata4+, rxdata4-).
Confirmation of any ** stack information is the first step, mainly to confirm the material, thickness and filling material of the stack
In order to save the computing resources of the computer and improve the efficiency, the key signal lines are cut, so as to save a lot of time and computing costs. In the clipping sub-design, we will draw a rectangle on the "user" layer (non-stack), and of course the clipping also supports polygons and self-expanding regions. The use of a rectangle in this design is cut in half after the following:
Set the type of the solder ball for FCHIP and BGA to cylinder, with a radius of 0075mm/0.33mm
After the build, it will look like this:
Next, add the following eight ports for the differential pair rxdata3+, rxdata3-, rxdata4+, and rxdata4-
The following steps are used to add them:
Solve settings, set the solution frequency to 25GHz, sweep range 0-25 ghz。Define the air box, where the horizontal and vertical directions are extended by 0025, the dielectric layer does not expand horizontally.
After solving, the differential pairs are defined as follows:
Looking at the results, you can see that the insertion loss of the two pairs is very small, as shown in the figure below
The return loss is as follows:
The electric field intensity distribution can also be observed across the package:
Summary: This analysis details how to analyze the signal quality of the differential pairs RXDATA3+, RXDATA3-, RXDATA4+, and RXDATA4- in BGA packages with the help of HFSS 3D Layout, including the setting of stacks, the addition of solder balls, and the configuration of ports.