Research on the standardization of new microelectronic packaging technology problems and improvement schemes
Li Yanlin, Chou Chen, Gan Yutian.
Gansu Forestry Vocational and Technical College).
Abstract:Electronic packaging is to wrap the bare IC silicon wafer with plastic to protect and make the external pins. The smaller the pin spacing, the more difficult it is to supply solder stably during reflow soldering, and the failure rate is very high. Multi-pin packaging is the mainstream in the future, so the technical requirements of microelectronic packaging should be adapted to multi-pin as much as possible. However, the packaging of chips has certain specifications, and if each packaging factory implements its own standards, it is obvious that the versatility of the chip will be greatly reduced, and it is impossible to create a prosperity in the semiconductor industry. In view of this, this paper discusses the problems of different electronic packaging technologies, analyzes the problems existing in electronic packaging technologies, and designs specific improvement plans to improve product reliability and reduce manufacturing costs and safety risks. In order to provide reference and guidance for the standardized production of microelectronic packaging technology.
INTRODUCTION. Microelectronic packaging is the bonding of one or more integrated circuits and flip chips to make them into electronic components or components with practical functions. This paper focuses on the safety and reliability of microelectronic packaging technology, through technical research, overcomes the key technical problems of high-density narrow-pitch small-pad copper wire bonding process, improves the process level of copper wire instead of gold wire in the field of small-pad and narrow-pitch IC chip packaging, promotes enterprise technological innovation and product independent development capabilities, narrows the gap with foreign packaging technology, and improves product quality and standardization level.
1 Microelectronic packaging technology and current situation.
Electronic packaging technology involves many disciplines, including materials science, electromagnetics, thermal management, micro-nano manufacturing, electronic devices and other specialties. With the gradual deepening of the research and development of three-dimensional integrated circuits by microelectronic packaging scientists, electronic packaging is changing from the traditional manufacturing mode to the system packaging (SOP - system on package SIP - system in package) and three-dimensional packaging (3D packaging) mode, and the advanced packaging technology of system packaging has begun to enter the market. The rapid development of electronic technology, the rapid upgrading, three-dimensional packaging (3D packaging) currently has no specific national technical standards, electronic packaging technology mostly adopts the technical standards of foreign research institutions. There are various forms of packaging, taking the most common dual in-line package (DIP, dual in-line package) as an example, dip8 means that there are 8 pins, and the length, spacing, width, etc. of the pins have strict standards to implement, and the packaging factory will only implement according to this standard, what if there are only 7 pads on the die now?Of course, it is still necessary to use dip8, just a pin is suspended, of course, it is impossible to design the number of pins at will, there are standards in all aspects of the semiconductor industry, "no rules are not a circle", microelectronic packaging technology from "primitive growth" to "mature development" needs to be organically standardized. By improving the relevant standards of microelectronic packaging technology, eliminating the differences in data format and data quality collected by different brands of microelectronic packaging technology hardware equipment, promoting the flow and sharing of information, and eliminating data silos have become an urgent need for the development and innovation of new microelectronic packaging technology.
1.1. New microelectronic packaging technology.
According to the requirements of the National Quality Supervision, Inspection and Quarantine Standards of the People's Republic of China, the scope of application of the original standard of the first slurry for microelectronics technology (GB T 17472-2008) has been expanded from the first slurry for thick film microelectronics technology to the best slurry for sintered and cured microelectronic technologyMore attention is paid to the weldability and weldability of the slurry. Generally speaking, microelectronic packaging is divided into **, which contains a number of contents of assembly and packaging. The scope of microelectronic packaging should include single-chip package (SCP) design and manufacturing, multi-chip package (MCM) design and manufacturing, chip post-packaging process, various package substrate design and manufacturing, chip interconnection and assembly, overall electrical, mechanical, thermal and reliability design of the package, packaging materials, packaging mold fixtures, and green packaging.
1.2. The new microelectronic packaging technology mainly includes the following types.
From the perspective of technology development, the key technologies of microelectronic packaging mainly include: (1) 3D packaging, on the basis of 2D packaging, a plurality of bare chips, packaging chips, multi-chip components and even discs are stacked and interconnected to form a three-dimensional package, which is called laminated 3D packaging (2) Solder Ball Array Package (BGA): Array package (BGA) is distributed under the package in an array of circular or cylindrical solder joints, resulting in increased assembly yield. The assembly can be coplanar welding, with high reliability;(3) Chip Scale Package (CSP) means chip scale packaging. CSP packaging allows for a ratio of more than 1:1 between the die area and the package area14, which is already quite close to the ideal situation of 1:1. Compared to BGA packages, CSP packages can increase storage capacity up to three times in the same space(4) System packaging (SIP) means that the function of the whole system is realized through packaging.
2 Analysis of microelectronic three-dimensional (3D) packaging technology.
2.1 The range of applications is not wide enough.
From the materials of microelectronic packaging technology, it can be seen that IC chips will develop in the direction of miniaturization, high performance and environmental protection requirements. The application range of microelectronic packaging technology is not wide enough, and in the past few years, it has been more than 208 pins, 256 pins, 304 pins, and the pitch is 05mm style, including spacing 0The QFPS of the 4mm style is mostly made of plastic and ceramic housings, and is usually suitable for high lead counts for various types of plastic devices.
2.2 Problems with the traditional copper wire bonding process.
Because the ultimate capacity of the traditional copper wire bonding process is the chip pad size of 50 m and the pad spacing is 60 m, the chip below this size can only use the gold wire process, and in the research process, in order to realize the reasonable replacement of this gold wire process, the following problems faced by small solder joints and narrow pitch copper wire bonding must be solved
First: copper wire bonding air balloon anti-oxidation technology;
Second: Prevent damage to copper wire bonding pads and control bonding technology for "aluminum spatter";
Third: the study of the bonding strength of the second solder joint;
Fourth: Copper wire bonding crack prevention and crater technology.
As the number of QFP package leads increases, the housing size increases dramatically, and the lead spacing can be further reduced in place of the increase in package size. Therefore, it is necessary to carry out research and development and technical improvement of high-density narrow-pitch packaging technology.
3. Specific improvement plans.
In order to solve the problems of microelectronic three-dimensional (3D) packaging technology, we have developed the following solutions: chips with a pad size of 38 m and a solder joint spacing of 43 mWire bonding material: ordinary copper wire, diameter 07mil。Stability studies of balloon sizes in different shielding gases were carried out.
3.1. Demonstration of technical route scheme.
3.1.1 Technical route.
Preliminary research, planning, determination of process flow, key technology research, engineering batch test, reliability assessment, risk batch production, small batch production, transfer to mass production.
3.1.2 Technical solutions.
In order to solve the above problems, we have formulated the following two solutions:
a.Option 1.
1) Research on anti-oxidation of copper wire bonding air balloons.
Hydrogen and nitrogen mixed shielding gas (flow rate: 04 ～0.7L min), 1000 air balloons were randomly selected and compared as follows: under the condition of N2+H2 shielding gas, 07mil ordinary copper wire burnt ball has 2003% of the air balloons have oxidized and peach-shaped balls on the surface, and the proportion of spherical defects such as asymmetrical balls, concave and convex balls, and hole balls reaches about 40%.
2) The first solder joint research experiment.
The results of the first solder joint research experiment were as follows: the copper wire bonding test was carried out on a chip with a solder plate size of 38 m and a solder joint spacing of 43 m, and the spherical defects (golf balls) accounted for 57%, and the bond strength (non-stick and aluminum loss) did not meet the quality requirements accounted for 677%；Figure 1 Random selection of 1000 balloons for mass analysisSpherical poor (01%) qualified (99.).9%）。
b.Option II.
Die pad size of 38 m 38 m and solder joint spacing of 43 m;
Wire bonding material: palladium-plated copper wire (PD coat cu wire), wire diameter is 07mil
1) Research on anti-oxidation of copper wire bonding air balloons.
Through the study of the stability of the size of the balloon in different shielding gases, the stability of the shape of the balloon in different protective devices (kits), and the influence of the flow rate of the shielding gas (froming gas) on the balloon, the copper wire bonding process standard has been reached.
2) The first solder joint research experiment.
The supporting equipment and matching capillary models were selected, the bonding process parameters were studied, and a set of ideal process parameters were finally determined through optimization tests such as power, impact force, x-y direction friction, rotational friction and other parameters. In addition, the joint chip manufacturer has improved the chip aluminum pad and established the copper wire process capability evaluation specification, so that the "aluminum spatter" and aluminum loss (peeling) of the pad can be effectively controlled, and finally meet the copper wire bonding process standard, and the experimental data of the first solder joint research is qualified (100%), as shown in Figure 2.
3) The second solder joint research experiment.
By optimizing the design of the capillary and selecting the appropriate capsulary model, the area of the second point contact and the thickness of the fishtail were increasedBy optimizing the line arc parameters, the fishtail and lead fit better;[2] By optimizing the welding parameters, the power and pressure of the second solder joint are increased, and if necessary, the grinding parameters are used to enhance the tension of the second solder joint and stabilize the wire tail lengthThrough the in-depth study of the bonding quality of the second solder joint, the copper wire bonding quality standard has been reached.
4) Copper wire bonding, crack prevention and crater research.
Through the anti-oxidation measures of copper wire, the control of the thickness and composition of the aluminum layer of the pad, and the research on the residual thickness of the aluminum pad to quickly confirm the copper wire bonding, the copper wire bonding cracks and craters have been effectively controlled.
ConclusionThrough the above research, the bonding ability of palladium-plated copper wire meets the process requirements, and the packaging requirements of high-density narrow pitch (43 m) small pad (38 m 38 m) IC chips are met. It has realized the standardization requirements of international standardization organizations such as SEMI (International Semiconductor Equipment and Materials Association) in the field of electronic packaging.
Conclusion. The solution uses a pad size of 38 m 38 m, a pad spacing of 43 m, and an aluminum pad thickness of 0A 9 m chip with a dielectric structure of FSG (fluorosilicate glass) was studied for copper wire bonding technology and a wire diameter of 0The process capability of 7mil high-reliability palladium-plated copper wire bonding process effectively guarantees the popularization and application of copper wire bonding packaging technology with small pad (38 m, 38 m) and narrow pitch (43 m) in LQFP, TQFP, ELQFP, and multi-turn QFN series products. Therefore, the design scheme can realize the technical indicators of the project, achieve the purpose and significance of the research, and provide technical support for standardized production.