Report Producer:Soochow**
The following is an excerpt from the original report.
1.The basic logic of advanced packaging is to increase the contact connection and solve the molar cap.
1.1.The nano process is difficult due to the quantum tunneling effect and high cost and low yield.
Due to the quantum tunneling effect and high cost and low yield, it is difficult to continue to improve the semiconductor manufacturing process. Since the invention of semiconductors and chips, the mainstream development direction has been an extension of Moore's Law, and the process of transistors has been continuously reduced. Reducing the process can reduce the size of the chip and increase the number of transistors on the chip, thereby improving the computing power, speed and performance of the chip, reducing power consumption and reducing costs. As the process technology moves to the nanometer level, the process is becoming more and more difficult to improve. The main obstacle comes from two sides.
The quantum tunneling effect (a type of short-channel effect) causes transistors to leak and chips to heat up, resulting in reduced chip performance and increased power consumption. Transistors work by applying a voltage to the gate and controlling the free charge in the channel to control the current breaking from the source to the drain, so that a 0 or 1 electrical signal is transmitted. When the voltage across the gate is 0, there is no free charge between the source and drain and cannot be energized; When there is a voltage in the right direction at both ends of the gate, there is a free charge between the source and drain, and the circuit is turned on. Process, which is the equivalent width of the gate or channel. When the channel width is reduced to a certain value, even if the voltage at both ends of the gate is 0, due to the random movement of the microscopic charge, there is still current flowing between the source and the drain, and the gate can no longer control the current on/off, the performance of the transistor is greatly reduced, and the heat generated by the "leakage" also increases the power consumption. Although this technical challenge has been made in some laboratories using new materials such as silicon carbide on a small scale, it has not yet been developed to the extent that it can be commercialized.
The R&D and manufacturing costs of advanced process chips remain high, but the yield rate is getting lower and lower. According to IBS and Gartner**, the design cost of chips has skyrocketed since entering the era of advanced processes, with the total design cost of 5nm reaching about $500 million. EUV lithography machines, masks, etc. are also increasing with the improvement of technical requirements, which increases the cost of chip foundry. At the same time, the yield rate of small-process chips is getting lower and lower. In 2023, it was reported that TSMC's 3nm yield rate is around 55%, and the halved yield rate also makes Apple negotiate a cheaper ** for the A17 processor chip built into its iPhone 15Pro. According to South Korea's Chosunbiz, both Samsung and TSMC struggle to exceed 60% of their 3nm semiconductor yields. Low yields obviously increase chip manufacturing costs and sales pressure. Based on this, mainstream manufacturers have turned to the use of advanced packaging technology, in order to reduce costs without sacrificing the high performance, small size, and low power consumption of small process chips, and make up for the difficulties of advanced manufacturing processes.
1.2.The iterative improvement of packaging technology is essentially to improve connection efficiency.
The iterative process of packaging technology is actually a process of continuous improvement of connection efficiency. In the era of traditional packaging, the package adopts through-hole insertion and surface mount methods, with low pin density, long transmission distance, small bandwidth, large resistance, and low transmission efficiency.
In the 90s of the 20th century, solder ball connection technology replaced leads, increasing contact area and pin density, reducing transmission distance and resistance, and thus reducing chip size. After 2000, it officially entered the era of advanced packaging. Wafer-level packaging reduces chip size, RDL, interposer, TSV and other technologies increase chip stack density and performance, and MicroBUMP and hybrid bonding technologies further reduce contact pitch and stack height. Iterations of packaging technology have increased pin density and bandwidth, reduced transmission distance and resistance, and virtually improved connection efficiency.
The intrinsic purpose of advanced packaging technology is to further increase the efficiency of the connection. In order to achieve the multi-function and large computing power obtained by high-density arrangement of small-volume transistors in small process chips, advanced packaging technology focuses on increasing the connection efficiency between chips (reducing signal delay and power consumption, increasing transmission rate) and improving the tightness of the connection. Increasing connection efficiency is generally achieved by reducing the contact distance to increase contact density, and by reducing the distance between chips and between chips and substrates.
The main advanced packaging technologies are: Rewiring Layer Technology (RDL). The IO contacts of the chip are usually located at or around the edges, and packaging directly will limit the connection due to missing or too dense leads. RDL technology rearranges the contacts of the die into the middle of a chip with a more spacious space, resulting in a larger and more number of bumps at the interface. Today's RDL technology is able to reduce the line spacing to a range of 1-10 m.
RDL technology enables the chip to support more pins after packaging to increase the computing power of the chip and the connection between chips.
This advantage is widely reflected in wafer-level packaging. Wafer-level packaging is mainly divided into fan-in wafer-level packaging (fan-inwlp) and fan-out wafer-level packaging (fan-outWLP), fan-in wafer-level packaging uses RDL to add contacts in the original area of the chip, and fan-out wafer-level packaging uses epoxy molding materials to appropriately expand the chip area, and at the same time uses RDL to extend the contacts in two dimensions.
RDL technology can replace the interposer, thereby reducing the connection distance and increasing the transmission rate. This technology enables direct connection between chips and substrates when vertically stacked packages, reducing the size of the packaging system and increasing the level of integration. TSMC's Info (IntegratedFan-Out) series packaging technology exemplifies this advantage. Unlike traditional vertically stacked advanced packaging technologies such as POPs, Info does not use a silicon interposer, but fan-out molding on the bottommost logic chip, and uses RDL technology to lay out the upper and lower connected circuits in the plastic area to connect the upper chip and the substrate. This connection is called TIVE (through-info-via). Info was first used in the iPhone 7 and helped TSMC receive all orders for Apple's A10 chips.
Through-silicon via technology (TSV). In order to reduce the transmission distance, people use stacked chips for packaging. Through-silicon via technology enables vertical interconnection between chips and between chips and substrates by punching through the solder joints of the chip and filling the vias with a metallic material (mainly copper). Compared to traditional tiled chips or wire-interconnect stacked chips, TSV's advanced packaging can significantly reduce connection distances and improve connection efficiency.
Through-silicon via technology is the key to achieving 2Key solutions for 5D and 3D packaging. TSMC's CODOS package.
A large number of TSV technologies are used, and their high speed and reliability make them the mainstream choice for high-performance chips such as AI (such as NVIDIA A100, H100, and AMD Mi300).
Bumping. This technology uses bumps instead of traditional leads, which increases the density of the IO contacts and reduces the transmission distance. Unlike wire bonding technology, which requires pads to be distributed around the chip, the surface-distributed bump array allows the IO contacts to be distributed in the middle of the chip, greatly improving space utilization and contact density. The use of flip clip technology and bumps to connect each chip vertically also shortens the circuit distance than wire bonding.
Bump technology is mainly divided into ball-grid-arraysolderball (BGABALL, diameter 0.).25-0.76mm)；flip-chip solderbump (fcbump), also known as controlledcallapsechipconnectionssolderjoint (c4solderjoint, 100-150 m diameter); Microbump (diameter can be as small as 2 m). When connecting the bumps, thermal compressionbonding is often used to melt the solder balls, cool them and fuse them, and fill them with underfills to improve the mechanical properties of the chip. Today, the diameter and spacing of the microbumps are shrinking.
Hybrid bonding technology can solve the problem of shrinking pitch, further improving contact density and connection efficiency. When the contact spacing is reduced to about 10 microns, the size of the solder ball is too small, and it is easy to completely react and deteriorate during the heating and melting process, reducing the conductivity. During the reflow of the planting balls, two adjacent solder balls are easy to touch together, resulting in chip failure. Hybrid bonding technology anneals the polished and concave cubump on the plane of the chip or wafer, so that the Cu is slightly expanded, and the two planes are completely bonded, which reduces the connection distance, improves the contact density, heat dissipation capacity, and signal transmission accuracy in a bumpless manner, thereby reducing energy consumption and improving efficiency. Hybrid bonding technology can increase the pin density of IO by a factor of 5-10 compared to micro-bumps. At present, hybrid bonding technology is mainly used for wafer-level packaging, in the wafer fabrication process, copper contacts are designed to connect two wafers, and after cutting, they become an integrated packaging module.
TSMC, Samsung, and Intel are leading the development of hybrid bonding technology. At present, TSMC's SOIC technology, Samsung's X-Cube technology, and Intel's FoverosDirect technology all use copper-to-copper direct bonding. AMD Ryzen™ 75800x3D Gaming Desktop Processors and Ryzen™ 7000X3D Premium Gaming Processors using SOICs are the first to achieve mass production.
1.2.1.The technical difficulty lies mainly in the lack of precision.
As the density of IO contacts continues to increase, so does the need for technical precision in advanced packaging. Take 12. For example, the wire distance, TSV through hole distance and thickness, bump diameter and spacing in the RDL rewiring layer are reduced, which requires continuous improvement of design and manufacturing technology and equipment. In the case of hybrid bonding, for example, since the contact planes need to be in full contact and the contact distances are extremely small (typically within 10 microns), it is necessary to ensure that the two plane contacts are strictly correlated during the design process (the error must not exceed 1 micron). In manufacturing, the chemical mechanical polishing (CMP) of the copper material after it has been deposited onto the die requires that the copper surface is very smooth and properly recessed to ensure that the flat surface is absolutely conformed after heating and melting. During the placement process, the die covered with fine copper contacts must be precisely targeted and not doped with dust particles.
Miniaturized and complex chips require more precision in the packaging process. Chip structures are becoming more complex, and vertically stacked packages increase chip integration, which can lead to higher costs and lower yields if defects cannot be detected in time during packaging. However, multi-layered structures, concealed circuits, and fragile structures make it difficult for inspection machines to reach and keep components intact. The challenges of advanced package failure analysis, illustrated in the figure below, illustrate the difficulty of defect inspection.
1.2.2.The upgrade logic is to increase connection efficiency and reduce manufacturing costs.
There are two main directions for upgrading and improving advanced packaging technology: first, to improve connection efficiency by increasing connection density, reducing connection distance, or improving material-related properties. In order to improve the connection efficiency, the main technological progress of increasing the connection density and reducing the connection distance has been made in 12 Discussion. At present, glass substrates are the representative technologies for improving the properties of contacts and electrical circuits.
Compared with organic substrates, glass substrates can withstand higher operating temperatures, and the coefficient of thermal expansion is close to that of silicon; It has higher flatness and structural stability; It has better optical properties and is conducive to fine lithography. Intel expects that the use of glass substrates in the package will increase the connection density by a factor of 10.
Another technological development direction of advanced packaging is to reduce costs. Advanced packaging requires high design accuracy and manufacturing equipment, so it is expensive. In order to increase the penetration rate of advanced packaging, manufacturers are trying to reduce the amount of materials used and use lower-cost materials and processes to alleviate cost pressures. Typical technologies that reduce packaging costs include Intel's EMIB (Embedded Multi-Chip Interconnect Bridge). EMIB belongs to 25D package, with traditional 2Compared with the 5D process, EMIB abandons the use of a whole silicon board as a silicon interposer and replaces it with a "silicon bridge", which only embeds a silicon "bridge" between the stacks of two chiplets to reduce the amount of silicon used. Vertical copper pillars in the substrate are used to power the upper chip, reducing the use of expensive TSV technology. Currently, TSMC's Info-LSI and CODOS-L technologies take a similar approach.
2.The increase in demand for computing power has led to a shortage of advanced packaging capacity.
2.1.Logic chips are the main demand point, and advanced packaging enables high-speed computing.
Advanced packaging technology is mainly used to improve the computing power of logic chips. Computing power usually refers to the number of computing tasks that a chip can perform per second. Advanced packaging mainly improves the computing power of logic chips in two aspects.
First, improve processor integration, thereby improving processor performance. Advanced packaging enables faster and tighter connections between multiple processors, thus enhancing the ability to process data in parallel or perform complex calculations. For example, the Apple M1 Ultra chip uses silicon interposer and silicon bridge technology to connect two Apple M1Max chips, which greatly improves performance.
Second, by solving the "memory wall" and "power consumption wall", the computing power of the computer can be improved. At present, the mainstream computer equipment adopts the von Neumann architecture, that is, the processor, memory, controller, etc. are separated from each other and perform their own duties.
Instructions and data need to be accessed from the same memory and transferred to and from the processor via the same bus. After the controller issues the calculation instructions, the computer first calls the required data from the memory to the processor, and then transmits the result to the memory when the operation is completed. Under the von Neumann architecture, data is read back and forth between memory and processor, creating a "memory wall" and a "power wall". On the one hand, when the amount of data is large, the bus bandwidth between the processor and the memory is limited, the bus is congested, and the data transmission delay increases. On the other hand, the repeated transmission of data consumes a lot of power. Intel's research shows that when the semiconductor process reaches 7nm, the power consumption for data transfer is as high as 35 pj bits, accounting for 63 percent of the total power consumption7%。Advanced packaging can increase connection bandwidth and reduce transmission power consumption by shortening the connection distance between the processor and memory and improving connection efficiency. For example, AMD, Hynix, and Nvidia are promoting HBM memory technology, which uses TSV and silicon interposers to vertically stack DRAM chips and package CPU GPUs with memory cells. HBM has become the memory solution of choice for advanced high-performance computing chips due to its higher bandwidth, smaller area (more than 50% reduction in total GPU area), and lower power consumption (more than 20% less power consumption in HBM2) than traditional memory GDDR5.
2.2.The supply of computing power exceeds demand, driving the growth of demand for advanced packaging.
The demand for computing power for AI large language models is growing exponentially. The global AI big oracle model mainly adopts the Transformer model architecture. The Transformer model is a non-serial neural network architecture that was originally used to perform context-based machine translation tasks. The Transformer symbolically adopts the "attentionlayers" structure, using the word embedding vector superposition encoding as the input, which can track the relationship between the texts in the context position, so as to produce the following text according to the text and text corpus at the input end, which has the advantages of being able to parallel operation, paying attention to contextual information, and strong expression ability.
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